FIR 滤波器的设计

说明：  用FPGA实现CNN算法，实现CNN加速(Realization of CNN Algorithms with FPGA)

hex_counter old project, please let me know if need any help

Kluwer academic the verilog hardware description language fith edition

access must be conf urr arr

FPGA的仿真实例，Verilog代码编写，过程详尽，代码易懂。第四个文档-FPGA simulation examples, Verilog coding, the process in detail, code easy to understand. The fourth document

VHDL_modelling_guidelines是vhdl建模开发的指导资料-VHDL modeling VHDL_modelling_guidelines is guiding the development of information

9对于输入密码锁的键，假设复位后七个灯显示" 0"，使用sw1、sw2、sw3、sw4 4，只需按下并松开任意sw1、sw2键，使七个灯显示值加" 1"，只要按下并松开任意sw3、sw4，将使七个灯显示值加" 2"

说明：  QUARTUS2 16.9 VHDL FPGA ENDAT2.2

可以产生正弦波，三角波、锯齿波、方波，要求频率1Hz-100kHz，步进1Hz，具有自动扫频功能； 正弦波的相位可调，方波的占空比可调； (Can generate sine wave, triangle wave, sawtooth wave and square wave, the required frequency of 1 hz- 100 KHZ, step 1 hz, with functions of automatic frequency sweep The phase adjustable sine wave, square wave duty ratio is adjustable )

DE2-70开发板中附带的控制面板，可以读取存储器中的数据，这个可以正常连接和读取，有好几版本的，有的不能用，而这个经过我亲自测试。(DE2-70 development board comes with a control panel, you can read the data in the memory, this can be properly connected and read, there are several versions, and some can not be used, and this after I personally tested.)