verilog program for 8

实验课的作业，包括半加器、全加器、加/减法器，使用逻辑图和VHDl描述，包括分析和报告。-experiment include the operation of a half adder, full adder, plus/subtraction device, and the use of logic diagram VHDl description, including analysis and reporting.

24,60,100进制的计数器，还有数字时钟，欢迎下载哦~-24,60,100 229 of the counter, digital clock also welcome to download oh ~

signaltap 中文说明，内容详细。 ALTERA signaltap USER GUIDE IN CHINESE(ALTERA signaltap USER GUIDE IN CHINESE)

vhdl的一个串行序列信号发生器的设计与实现-vhdl sequence of a Serial Signal Generator Design and Implementation

dc的应用规范，以及一些基础的操作指导，注意事项等(dc application specification, as well as some basic instructions, precautions, etc.)

基于研华采集卡的FIFO双缓存区高速数据采集(FIFO DAQ)

步进电机驱动，32等级速度，带加减速度控制。verilog编写。(step motor driver,32 level speed.)

UVM 1.2 golden code, (code for UVM, )

实现arm与fpga之间通过gpmc总线通信(the device of fpga)

4*4按键扫描电路，用数码管显示0~F，基于VHDL语言设计，包括按键扫描，数码管扫描，数码管显示，按键消抖等代码