verilog program for 8

fpga_sopc_enc28j60_tcp_ip_测试，源码程序包，本人测试通过！(Fpga_sopc_enc28j60_tcp_ip_ test, the source code packets, I test through!)

how to use step motor control

有关于SD卡的音频部分！希望对大家有用！-SD cards have on the audio portion! Hope useful for everyone!

基于FPGA的数字系统设计,包含原理、工程应用和案例。(FPGA-based digital system design, including theory, engineering applications and cases.)

FPGA来实现数据采集，AD采用TI公司的THS1206，高速并行AD，内含16字FIFO，降低硬件复杂度。(FPGA to realize data acquisition, AD using TI company s THS1206, high-speed parallel AD, containing the 16-character FIFO, to reduce hardware complexity.)

基于FPGA设计的经典打砖块小游戏。游戏简单易玩。(FPGA design based on the classic Arkanoid game. Game easy to play.)

dsp与fpga通信的verilog程序，强烈推荐欢迎参考(dsp and fpga verilog communication program, it is strongly recommended to welcome reference)

rs422标准通讯模块 异步收发 verilog语言编写(rs422 standard communication module asynchronous receiver verilog language)

说明：  使用Verilog编写的24位定时器，具有apb 总线接口，可以设置工作方式和计数初值。(The 24-bit timer written by Verilog has APB bus interface, which can set working mode and count initial value.)

简单的apb i2s接口，verilog代码，包括rtl实现和testbench(apb i2s interface . coded by Verilog. including rtl and testbench)