This is achieved using VHDL positive and negative pulse width modulator, the sam...

VHDL与源代码包-and VHDL source code

用verilog编写的分辨率提高的源代码 采用双线性插值(Written resolution with the verilog source code to improve the use of bilinear interpolation)

是codic算法实现atan的C程序，包括定点和浮点程序，已经通过验证。(Atan is codic algorithm of C procedures, including fixed-point and floating-point procedures, has been validated.)

说明：  fpga版本的数码管动态扫描程序，可供学习(FPGA version of the digital tube dynamic scanning program for learning)

在数字通信中，通常直接从接收到的数字信号中提取位同步信号，这种直接法按其提取同步信号的方式，大致可分为滤波法和锁相法。锁相法是指利用锁相环来提取位同步信号的方法，本设计方案就是基于锁相环的位同步提取方法，能够比较快速地提取位同步时钟，并且设计简单，方便修改参数。采用Quartus II设计软件对系统进行了仿真试验，并用Altera的Cyclone II系列FPGA芯片Ep2c5予以实现。(In digital communication, usually from receiving directly in digital signal extracted a synchronized signal, the direct method according to the extraction synchronized signal way, can be roughly divided into filtering method and phase lock method. Phase lock method is using of phase locked loop to extract a synchronized signal method, the design scheme is based on phase locked loop of a synchronous extraction method and can be quickly extract a synchronous clock, and design simple, convenient modification parameter. The Quartus II design software of the system, and the simulation test Altera Cyclone II FPGA chip to achieve Ep2c5 series.)

VHDL入门级好教材《VHDL开发精解与实例剖析》(VHDL development solution with fine examples of analysis)

vedic multiplication

FPGA跑马灯程序,基于CPLD1270开发板的运用程序-Marquee program FPGA-based development board CPLD1270 the use of procedures

RS译码的Euclid算法及其FPGA实现，并通过仿真器的出结果，对于设计ＲＳ译码很有帮助-RS decoding Euclid algorithm and its FPGA implementation, and through the simulator results are helpful for the design of RS decoder

使用VHDL语言实现了FPGA与DAC5688进行SPI通信更改寄存器值(The FPGA using VHDL language with the DAC5688 SPI communication to change the register value)