基于alteraCPLD芯片的VHDL点阵滚动显示源代码

四路控制抢答器模块设计 他的基本功能是，在四组参赛的情况下，首先抢答的发出抢答信号，此时其它抢答电路失去控制作用，在优先抢答的要在固定时间进行答题，否则直接扣一分

将BT656数据流转换成RGB图像格式的数据(Converting BT656 data stream into RGB image format)

用VIVADO软件编写的，实现以太网芯片88E1510中的mdio控制模块代码，并且含有VIO仿真文件(Written in VIVADO software, the realization of the Ethernet chip 88 e1510 mdio control module of code, and contains the VIO simulation file)

vhdl的3-8译码器-instantiate the 3-8 decoder

user_logic_VGA_Controller，适合于DE2开发板，把这个文件夹放在工程目录之中，就可以在SOPC里直接添加VGA_Controller IP核了，很方便使用。-user_logic_VGA_Controller. suitable for Dictyophora development board, this folder on the project directory, it can be added directly SOPC Lane VGA_Controller IP core, very convenient to use.

first in first out 的说明文档以及时序图 对学习FIFO很有帮助(first in first out the documentation and the timing diagram helpful in learning FIFO)

适用于NIOS II的1024点FFT C算法( 1024-point FFT C algorithm for NIOS II)

定时器的编程，vhdl语言，可以实现24时制定时器-Timer programming, vhdl language, can be achieved when the system timer 24

verilog例子资源，对于初学者很有帮助。-verilog examples of resources are very useful for beginners.

说明：  “基于 ROM 的 LCD图片显示实验 ”中利用 FPGA 片上存储资源存储图片，并通过 LCD接口将图片显示到 LCD屏幕上。但是由于 FPGA 片上存储资源有限，只能存储分辨率较小的图片(In the experiment of LCD image display based on ROM, FPGA on-chip storage resources are used to store pictures, and the pictures are displayed on LCD screen through LCD interface. However, due to the limited on-chip memory resources of FPGA, it can only store images with smaller resolution)