基于alteraCPLD芯片的VHDL点阵滚动显示源代码

Brazo robotico proyecto para laboratorio

设计一个十进制计数器模块，输入端口包括 reset、up_enable 和 clk，输出端口为 count 和 bcd，当 reset 有效时（低电平），bcd 和 count 输出清零，当 up_enable 有效时（高电 平），计数模块开始计数（clk 脉冲数），bcd 为计数输出，当计数为 9 时，count 输出一 个脉冲（一个 clk周期的高电平，时间上与“bcd=9”时对齐）(Design of a decimal counter module, input port, including the reset up_enable clk, output port for the count and bcd, when reset is active (low), the bcd and count output cleared up_enable active (high), count module starts counting the (the CLK pulse number), the BCD count output when the count 9, the count output of the high level, the time of a pulse (a clk cycle with " bcd = 9" when aligned))

利用Cadence Allegro PCB SI进行SI仿真分析(Performed using the Cadence Allegro PCB SI SI simulation analysis)

matlab code for communication

说明：  adfvff f fdfs f dvdsz dz vdzsvd hdfdgvaz

manchester_verilog源代码(manchester_verilog source code)

文件描述的是SDH 指针处理和系统同步代码 veriolg(SDH pointer processing and system synchronization code veriolg of file Description)

忆阻器的PSPICE仿真，是忆阻器的宏模型，适合于cadence16.5版本(memristor PSPICE simulation)

IS611v25616在NIOS II 下的驱动-NIOS II in IS611v25616 under the driver

在VHDL结构体中用于描述逻辑功能和电路结构的语句分为顺序语句和并行语句两部分，顺序语句的执行方式十分类似于普通软件语言的程序执行方式，都是按照语句的前后排列方式顺序执行的。(VHDL structure in the body used to describe the logic function and circuit structure of the order of statements and expressions are divided into two parts in parallel statement, modalities for the implementation of the order of statement is very similar to ordinary language software program implementation, are in accordance with the statements before and after the arrangement of the order implementation.)