基于alteraCPLD芯片的VHDL点阵滚动显示源代码

一个比较有参考价值的sram IP核，对SOPC感兴趣的人士有一定的指导意义！该程序是采用avalon总线，可以直接内嵌进SOPC Builder。-A comparison reference value has sram IP core, on the SOPC interested people have a certain guide! The procedure is used avalon bus, can be directly embedded into the SOPC Builder.

logic lock 的vhdl源码，altera平台适用。-logic lock the VHDL source code, altera platform.

说明：  设计了六相感应电机的控还原 制平台的硬件结构及其各个组成部分,控制平台结构主要由DSP控制系统和主驱动电路系统以及检测电路系统组成。控制系统采用TI公司的TMS320F2812快速DSP控制芯片。 (This paper designs the hardware structure of the six-phase motor control system and introduces every component. The control platform consists of DSP control system, main drive circuit system and detection circuit system .The control system adopts TMS320F2812 DSP chip of TI Company. 更多还原 )

数字钟vhdl主要分为正常显示与报时功能(Digital clock vhdl)

verilog code for apb to ahb convert

数字钟电路的实现，可以24小时计时，可调整时间！(Digital clock circuit implementation, a 24-hour timer, adjustable time!)

说明：  生成一个M伪随机序列码，在ISE平台上可跑通(Generate an M Pseudo-Random Sequence Code which runs on ISE platform)

基于FPGA实现IIR滤波器的程序，用VERILOG编程语言实现(The program based on the FPGA implementation of the IIR filter is implemented in the VERILOG programming language)

QuartusII简介手册+中文版 本手册针对的读者是 Quartus II 软件的初学者，它概述了可编程逻辑设计中 Quartus II 软件的功能。 不过，本手册并不是 Quartus II 软件的详尽参考手 册。 相反，本手册只是一本指导书，它解释软件的功能以及显示这些功能如 何帮助您进行 FPGA 和 CPLD 设计。-QuartusII brochure+ Chinese version of the manual is aimed at readers of Quartus II software for beginners, it provides an overview of programmable logic design in Quartus II software. However, this manual is not the Quartus II software, a detailed reference manual. Instead, this manual is a guide book, which explained the functions of the software and show how these features help you to FPGA and CPLD design.

useful VHDL document for programmer