基于alteraCPLD芯片的VHDL点阵滚动显示源代码

SRAM 读写实验，SRAM存储器的读写操作，Verilog源码有助于提高代码coding能力。使用例程。(SRAM write and read)

simple code based on verilog shifter , cla ,clg , ALU , PC

fpga实验板上16*16点阵显示汉字的程序-翻译结果fpga实验板上16*16点阵显示汉字的程序(Experimental fpga board 16* 16 dot matrix display Chinese program- translation results fpga experimental board 16* 16 dot matrix display Chinese characters in the program)

使用FPGA的FIFO，状态机，乒乓操作等实现了异步UART。-The use of FPGA-FIFO, state machine, ping-pong operation to achieve the asynchronous UART.

CSC RGB2YUV Verilog source code

说明：  高速宽带数字调制技术的研究，该论文也是非常经典的，希望对大家有帮助(High-speed broadband digital modulation technology, the paper is also very classic, I hope all of you help)

SDIO slave, written in verilog, does not support SPI mode.

反应速度测试小游戏，最小外设cpld游戏，带设计说明书(Reaction speed test games, the minimum peripheral cpld game, with design specifications)

固定的 128 点复杂 FFT 或 64/8/16 点

说明：  使用vivado和Xilinx开发板实现抢答器，开发板为Xilinx Artix-7(Using vivado and Xilinx development board to achieve the responder, the development board is Xilinx artix-7)