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由VHDL 语言实现的D触发器利用的是QUARTUES环境已经得到验证
由VHDL 语言实现的D触发器利用的是QUARTUES环境已经得到验证-By the VHDL language using the D flip-flop is QUARTUES environment has been tested
- 2022-05-08 21:19:33下载
- 积分:1
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lisa-vhdl2va
通过modelsim仿真检测matlab生成滤波器效果。(Generate the filter through matlab and simulated by modelsim.)
- 2013-12-12 11:17:18下载
- 积分:1
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PIP
基于FPGA的画中画处理PDF技术文档,采用SD卡里图片读出来做为底图,然后再图上叠加另外一个图片或者视频(Based on the FPGA picture in picture processing PDF technical documentation
)
- 2014-07-10 17:56:04下载
- 积分:1
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Xilinx CPLD源代码,使用XC9500系列CPLD,驱动液晶
Xilinx CPLD源代码,使用XC9500系列CPLD,驱动液晶-Xilinx CPLD source code, use the XC9500 series CPLD, LCD Driver
- 2023-03-07 15:05:03下载
- 积分:1
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is done in the laboratory in the loss of 60 counts, and LED show.
是我们在在实验室做的摸60计数,并用LED显示出来。-is done in the laboratory in the loss of 60 counts, and LED show.
- 2022-03-21 19:17:50下载
- 积分:1
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FFT处理器,FPGA的设计,适用于信号处理技术参考…
FFT处理器的FPGA设计方法,适合做信号处理的技术人员参考,用FPGA实现-FFT processor, FPGA design, suitable for signal processing technology for reference, using FPGA to achieve
- 2022-12-05 04:55:03下载
- 积分:1
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This is the design of the divider module EDA. Can achieve three different freque...
此为EDA设计的分频器模块。可以实现三种不同的频率信号,可以通过使用者自由设置频率大小-This is the design of the divider module EDA. Can achieve three different frequency signals, users can freely set the frequency of the size of
- 2022-07-22 16:48:57下载
- 积分:1
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verilog
说明: verilog开发的经典教材,详细介绍了语法,常见历程,以及通用的程序段(verilog development of the classic materials, detailed information on syntax, common history, as well as the common program segment)
- 2010-03-18 12:11:18下载
- 积分:1
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指令式ROM核
代码风格非常好,容易看懂,移植性高
- 2022-01-25 22:47:21下载
- 积分:1
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FPGA RAND 生成伪随机数
FPGA生成伪随机数,希望对加密的童鞋有用(FPGA generates pseudo-random numbers, we want to be useful)
- 2013-08-05 16:43:55下载
- 积分:1