一个异步FIFO的verilog实现论文

verilog 代码实现串并转换，有延迟(Verilog code and string conversion, delay)

说明：  DAC3283 寄存器初始化，SPI驱动(Dac3283 register initialization, SPI drive)

FPGA编程，经过团体奋战完成，全是底层的IIc和sci通信，完整版。(FPGA programming, after groups fight to the finish, all underlying SCI and IIc communication, full version)

说明：  Ovo sto saljem je tutorijal 7 sa vhdlom

这是用verilog语言实现的1024点ff程序t-This is achieved using Verilog 1024 language ff procedures point t

数字时钟，包括流程图以及编码和完整的实验报告，内容详细丰富。(Digital clock, including flowcharts, and coding and a full lab report, detailed and rich.)

利用verilog语言设计公共电话共包括以下几个状态：挂机、待机、身份确认、修改密码、通话等五个状态。内含详细的源码以及设计过程、模块-The use of public telephones were verilog language design include the following states: hang up, standby, identification, change passwords, call the five states. Includes a detailed source code as well as the design process, the module

程序设置了fpga 的 5x5点阵驱动程序，代码相对比较简洁，这个程序可以作为fpga输出控制，驱动稳压芯片工作，进而点灯

基于DSP28335的产生ADc采样的程序(Program for generating ADC sampling based on DSP28335)

32位乘以32位乘法器，由datapath 和控制中心组成，输出64位结果(32bits by 32 bits multiplier )