一个异步FIFO的verilog实现论文

定时器加数码管显示源码，以及test bench测试模块源码，经modelsim仿真结果正确(Timer plus digital display source code, and test bench test module source code, by modelsim simulation results are correct)

七人表决器，当有四人或四人以上的人同意是，表决通过。每个裁判控制一个开关，高电平表同意，在quartusII上用全加器来实现，当表决通过时，实验箱上的LED灯亮

8051core-Verilog FPGA

I2C控制器的源代码，Verilog HDL语言编写，可以直接调用-I2C controller source code, Verilog HDL language, you can directly call

数字系统设计报告，多功能电子钟，显示年月日星期时分秒，及校时等功能(Digital system design report, multi-functional electronic bell, show date when the minutes and seconds a week, and school functions when)

Complete Successive approximation Analog to digital converter along with the source code

bt1120设计方案，描述了具体的方案设计以及整体的架构设计(Bt1120 design scheme, describes the specific scheme design and the overall architectural design)

通信中加扰/解扰算法。FPGA源代码，verilogHDL语言实现，包含测试程序。(Perturbation/perturbation algorithm. FPGA source code, verilogHDL language implementation, including test procedures.)

in this code very useful for designing real number concept

说明：  使用verilog语言实现H.265压缩算法，能够实现实时视频数据的压缩传输(Using Verilog language to realize h.265 compression algorithm can realize the compression and transmission of real-time video data)