complete with verilog language development USB2.0 IP source code, including docu...

VHDL源代码包-VHDL source code

在学习verilog 中与遇到一些列问题的整理。(this Documentation is about the problem about verilog which is meeted when i was learn FPGA)

stepper motor vhdl pin assignments and code

i2c master ip for altera nios, add in qsys

用verilog语言的实现FIFO存储器，以先进先出的方式处理数据(The FIFO memory is implemented in Verilog language, and data is processed in FIFO)

uart的vhdl实现，包含完整quartus工程文件，相信会有较大帮助-uart vhdl quartus

八位并行数据转换为串行数据依时钟信号串行输出(Eight bit parallel data to serial data)

CPU代码-VHDL语言，实现了CPU的基本功能。-CPU code-VHDL language, the realization of the basic functions of the CPU.

串口收发程序，成功通过仿真，可以用来学习(Serial transceiver,It is successful through simulation and can be used to learn)

FIR滤波器：自定滤波器的类型（低通，高通或带通）、设计指标（通带截止频率、通带波纹、阻带截止频率、阻带衰减） 1、根据指标选择合适的窗函数，用窗口设计法设计符合指标的FIR滤波器；并验证其性能是否满足预定指标。 (FIR filters: Custom filter types (low pass, high pass or band-pass), design specifications (passband cutoff frequency, passband ripple, stopband cutoff frequency, stopband attenuation) 1, according to indicators choose the right window function, using the window design method of FIR filter designed to meet the targets and verify that its performance meets the set targets.)