VHDL与Verilog的比较

this is code verilog

basic verilog code on siso, piso, sipo

xilinx ise开发环境中fft IP核调用，仿真(Xilinx ise development environment FFT IP core call, simulation)

It is then register ( shifter) PISO ( Parallel - in, serial - out)-It is then register ( shifter) PISO ( Parallel- in, serial- out)

此两文件是在MAXplusII环境下开发并运行通过的VHDL文件，实现了并串口转换功能。-this document is in two MAXplusII environment through the development and operation of the VHDL documents, and the realization of serial conversion function.

直接数字式频率合成器DDS设计、Verilog。 产生的信号可以是正弦波或方波、三角波、锯齿波等，自选。 采用DDS技术，将所需生成的波形写入ROM中，按照相位累加原理合成任意波形。 此方案得到的波形稳定，精度高，产生波形频率范围大，容易产生高频。 本实验在设计的模块中，包含以下功能： （1）通过 freq 信号输入需要的频率的值； （2）通过 wave_sel 信号选择所需的波形； （3）通过 amp_adj 信号选择波形放大的倍数。(DDS design of direct digital frequency synthesizer, Verilog. The generated signal can be sinusoidal or square wave, triangular wave, sawtooth wave and so on, optional. By using DDS technology, the required waveforms are written into ROM, and arbitrary waveforms are synthesized according to the principle of phase accumulation. The waveform obtained by this scheme is stable, accurate and easy to generate high frequency waveform. This experiment includes the following functions in the designed module: (1) Input the required frequency value through freq signal; (2) Choosing the required waveform by wave_sel signal; (3) Select the multiplier of waveform amplification by amp_adj signal.)

have a good documenty

multiplexerwe 的 vhdl 程序可以写也像 thisits 非常简单的代码为 beginers 了解 4： 1 多路复用器

比较适合初学学者，而且比较基础。描述的不全面，先看看吧-it‘s best book for beginner！

(7,4)循环码的verilog编码程序，（7，4）循环码的verilog译码程序((7,4) cyclic code Verilog coding procedures, (7,4) cyclic code the verilog decoding procedure)