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altera嵌入式设计大赛文章,车载cots设计实现
altera嵌入式设计大赛文章,车载cots设计实现-Embedded Design Contest altera article, cots Car Design
- 2022-05-20 14:21:28下载
- 积分:1
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MIPS_LANG
说明: verilog实现misp架构,并且支持modelsim仿真(Verilog implements MISP architecture and supports Modelsim simulation)
- 2020-06-18 04:40:02下载
- 积分:1
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VHDL-the-count
利用VHDL 硬件描述语言设计一个0~9999 的加法计数器。根据一定频率的触发
时钟,计数器进行加计数,并利用数码管进行显示,当计数到9999 时,从0 开始重新计数(Use of VHDL hardware description language design a 0 ~ 9999 addition counter. According to a certain frequency of the trigger
The clock, counter add count, and use digital pipes to show that when the count to 9999, starting from 0 to count
)
- 2012-01-13 14:01:38下载
- 积分:1
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based on VHDL development mcu with external device interface, mcu solve the high
基于VHDL语言开发的mcu与外部器件的接口程序,解决了高速mcu与低速外部器件的接口问题。-based on VHDL development mcu with external device interface, mcu solve the high-speed and low-speed external device interface.
- 2023-06-24 09:15:02下载
- 积分:1
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文章论述如何将向modelsim中添加仿真库,包括添加xilinx,altera,actel公司的仿真库的方法...
文章论述如何将向modelsim中添加仿真库,包括添加xilinx,altera,actel公司的仿真库的方法-Article on how to add ModelSim simulation library, including the add xilinx, altera, actel the company
- 2022-02-13 01:04:22下载
- 积分:1
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PN-(2)
伪随机序列FPGA 通过仿真 M3000(Pseudo-random sequence M3000 FPGA simulation)
- 2011-06-09 13:40:00下载
- 积分:1
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sram_sp_hse_8kx8
SRAM 8K*8 芯片存储器 芯片存储器 芯片存储器(SRAM 8K*8
Chip memory
Chip memory)
- 2018-08-26 18:50:04下载
- 积分:1
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verilog___UART
Verilog 编写的串口通信模块 带测试代码(Verilog prepared by the serial communication module with a test code)
- 2012-05-24 20:38:27下载
- 积分:1
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4
通过监测工作状态实现带有IIC通讯功能的数据发送接收(to implement the sending and receiving data function of iic
communication )
- 2013-09-29 09:51:55下载
- 积分:1
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xilinx of ddr sdram controller documentation
xilinx的ddr sdram控制器文档-xilinx of ddr sdram controller documentation
- 2023-04-17 06:40:03下载
- 积分:1