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uart
用Verilog HDL,实现的FPGA串口调试程序,已经在硬件上调试成功(With Verilog HDL, FPGA serial debugger implemented in hardware debugging has been successful)
- 2015-07-23 15:24:12下载
- 积分:1
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通过VHDL语言的例子,乒乓球运动的FPGA原型样机(2章)是
应用背景FPGA原型的VHDL例子提供一系列清晰,易于遵循的快速代码开发模板;大量的实际例子来说明和强化的概念和设计技术;现实可实施的项目和测试在Xilinx原型板;深入探索和Xilinx PicoBlaze软核微处理器。关键技术本书采用“做中学”介绍VHDL和FPGA技术的概念和设计人员通过一系列的实验方法。
- 2022-08-13 14:19:44下载
- 积分:1
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6264
6264是一种8K×8的静态存储器.SRAM 的典型芯片有2KB 的6116、8KB 的6264 以及32KB的62256,其中6264 芯片应用最为广泛.(6264 is the 62256 typical chip SRAM.SRAM a 8K* 8 with 2KB 6116, 8KB 6264 and 32KB 6264 chip, which is most widely used.
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- 2015-02-01 13:28:11下载
- 积分:1
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用VERILOG语言编写的电子琴程序.用GW48教学实验箱仿真的
用VERILOG语言编写的电子琴程序.用GW48教学实验箱仿真的-Using Verilog language organ procedures. GW48 teaching experiment with simulation boxes
- 2022-03-01 23:12:48下载
- 积分:1
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design-of-CAN-based-on-VHDL
基于Verilog+HDL设计CAN控制器,详细介绍各功能模块的设计。本论文的重点是CAN总线通信控制器的前端设计。即用Verilog HDL语言完成CAN协议的数据链路层的RTL级设计,实现其功能,并且能够在FPGA开发平台Quartos上通过仿真验证,证明其正确性(Verilog+ HDL-based design of CAN controller, detailed design of each functional module. This paper focuses on the CAN bus communication controller front-end design. Verilog HDL language that is used to complete the data link layer CAN protocol the RTL-level design, to achieve its function, and can be on the FPGA development platform Quartos by simulation to prove its correctness)
- 2011-07-22 15:22:27下载
- 积分:1
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A brief introduction of direct digital frequency synthesis (DD S), the use of DD...
简单介绍了直接数字频率合成技术(DD S),利用DDS设计任意
波形发生器,其能够产生矩形波、正弦波、三角波、锯齿波等多种波形 -A brief introduction of direct digital frequency synthesis (DD S), the use of DDS design of arbitrary waveform generator, which can produce rectangular wave, sine wave, triangle wave, sawtooth waveform etc.
- 2022-04-02 02:31:45下载
- 积分:1
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CH2CH1VHDL 数字电路参考书所有程序3
CH2CH1VHDL 数字电路参考书所有程序3-CH2CH1VHDL digital circuit reference all three procedures
- 2022-05-29 17:53:40下载
- 积分:1
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serial port simulated programme of lattice
lattice的串口仿真的程序- serial port simulated programme of lattice
- 2023-04-29 09:40:03下载
- 积分:1
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ASYNC_FIFO_SYNTH
This file contains async fifo design
- 2014-03-01 20:48:22下载
- 积分:1
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In Altera
在Altera的FPGA开发板上运行第一个FPGA程序,以后我还会陆续发布这方面的代码-In Altera
- 2022-03-11 01:12:51下载
- 积分:1