xilinx of ddr sdram controller documentation

这是基数 4 修改 Booth 型乘法器为 8 位。它可以用于任何大小的操作数的乘法......

FPGA Boards - Spartan 3 E Starter Kit

音频spdif格式编解码，可以将音频格式在i2s dsd以及spdif之间转换(Spdif audio codec)

用verilog编程的TCON模块（时序控制器）的程序(Verilog programming module with TCON (timing controller) program)

FPGA代码，包含地址译码模块、16位锁存器、AD片选、死区及滤除窄脉冲、过流和短路保护、解除脉冲封锁模块、PWM模块、PWM选择 (FPGA code, including the address decoder module 16 latches, AD chip select, filter out the dead and narrow pulse, overcurrent and short circuit protection, lifting the blockade pulse module, PWM module, PWM selection)

说明：  MATLAB的SIMULINK和FPGA联合设计滤波器等，摆脱了传统的代码设计。(MATLAB's SIMULINK and FPGA jointly design filters and so on, and get rid of the traditional code design.)

A controller for DDR2 on FPGA with vhdl, content testbench, model and textfile-generation/data-detection using python.

是codic算法实现atan的C程序，包括定点和浮点程序，已经通过验证。(Atan is codic algorithm of C procedures, including fixed-point and floating-point procedures, has been validated.)

《Verilog HDL 程序设计教程》6-"Verilog HDL Design Guide" 6

计数器是数字系统中使用最多的时序电路，它不仅能用于对时钟脉冲计数，还可以用于分频、定时、产生节拍脉冲和脉冲序列以及进行数字运算等。(Counter is the most frequently used sequential circuit in digital system. It can be used not only for counting clock pulses, but also for frequency division, timing, generating beat pulses and pulse sequences, and performing digital operations.)