xilinx of ddr sdram controller documentation

This an interpolating by 2 half-band filter with 79 taps (40 none-zero coefficients).

ebook verilog HDL programming book

从零开始的Xilinx DDR3 控制程序编写教程，利用MIS IP核通过自编逻辑实现对DDR3的读写，强烈推荐(This is a zero to start Xilinx DDR3 control program written tutorial, the use of MIS IP kernel through the self compiled logic to achieve DDR3 reading and writing, strongly recommended.)

说明：  学习vhdl硬件描述语言的一些例子的原代码(VHDL hardware description language to learn some examples of the original code)

vga接口的工程实现，基于altera环境，需要的可以-vga interface engineering implementation, based on altera environment, need to take a look at

build synthesizer on a de2 dev fpga board

数字钟的实现 FPGA上运行 VHDL编写-Digital clock running on the FPGA to achieve the preparation of VHDL

这是OFDM调制matlab的程序，中间详细描述了调制的过程，希望对大家有用。(This is the OFDM modulation matlab procedures, a detailed description of the intermediate modulation process, I hope useful.)

对于在dsb系统中进行通信所以实现的硬件仿真和验证，对大家有一定的帮助谢谢

自己写得一个关于sine（32X24）的程序-own written on a sine (32X24) procedures