两个加法器和乘法器与并行处理的使用…

利用IIC接口的4路 ADC max1037，采集思路信号，通过在FPGA内部的构建DeltaSigma DAC软核，在VGA液晶显示屏上显示波形。 (IIC interface 4-way ADC max1037, collecting ideas signal the FPGA internal build DeltaSigma DAC soft-core VGA LCD display waveforms.)

Protocol Buffers - Google s data interchange format.

说明：  Verilog学习文档，介绍基本知识点，语言要素(for learning Verilog)

异步FIFO 设计源代码，内涵完整的verilog源代码和测试代码。-Source code for asyn_fifo using verilog language.

说明：  用于FPGA的I2S接收模块，仅供学习和参考(audio-i2s receive.use fpga.)

高速计算机旋转坐标算法的硬件实现，用于快速傅里叶算法的核心单元-Rotating coordinates high-speed computer hardware algorithm for fast Fourier algorithm is the core unit

FPGA SPI 主要模块全部涵盖 时序解释 与DSP通信(FPGA SPI Timing interpretation covering all main modules communicate with the DSP)

本程序实现流水线功能，您可根据自己需要更改参数，试用芯片xilinx，用verilog语言编写(This program implements the pipeline, you may be required to change the parameters according to their own try xilinx chip with verilog language)

说明：  RISC 5级流水线CPU，带HAZARD处理(RISC 5 pipeline CPU with HAZARD processing)

FSM_test for textbanch in vhdl-FSM_test