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list_ch06_02_debounce
Eliminate the program of key bounce
- 2012-12-23 00:22:42下载
- 积分:1
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rtl
基于脉动结构的有限域乘法器,verilog代码(Based on the pulse of the structure of finite field multipliers, verilog code)
- 2010-01-04 11:48:50下载
- 积分:1
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用VerilogHDL进行频率生成器。
yong VerilogHDL yu yan bianxie de pinlv fa sheng qi,shi yong ISE ruan jian da kai.-Used VerilogHDL to make a frequency builder.
- 2022-01-21 03:50:48下载
- 积分:1
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formal_verification
说明: 现在最流行的RTL设计方法之一,本书为全球流行的设计入门书籍(One of the most popular RTL design methods nowadays, this book is an introductory book for popular design all over the world.)
- 2020-06-23 22:00:02下载
- 积分:1
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galois
example of BCH and RS codecs
- 2009-06-10 11:26:17下载
- 积分:1
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Altera-FPGA_CPLD-design-Advanced
《Altera FPGA_CPLD设计 高级篇》详细介绍FPGA应用于高级特性,LogicLock设计,时序约束,设计优化,高级工具及系统级设计技术,是深入学习FPGA的重要材料(" Altera FPGA_CPLD advanced part design" details FPGA used in advanced features, LogicLock design, timing constraints, design optimization, system-level design tools and advanced technology, in-depth study is an important material for FPGA)
- 2017-03-08 19:47:32下载
- 积分:1
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2003101190493221
还好用,大家一起来看下,不错的图书管理软件啊 ,呵呵(Fortunately with, everyone look, the good library management software, ah, huh, huh)
- 2010-09-14 13:08:40下载
- 积分:1
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一个基于VerilogHDL语言的16位的booth算法的乘法器及其测试代码
一个基于VerilogHDL语言的16位的booth算法的乘法器及其测试代码-VerilogHDL language based on the 16-bit multiplier of the booth algorithm and test code
- 2022-02-07 12:03:36下载
- 积分:1
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altera EP1C6Q240C6开发板原理图
altera EP1C6Q240C6开发板原理图-altera EP1C6Q240C6 SCH
- 2022-12-08 05:45:03下载
- 积分:1
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StopWatch
This is a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.
- 2013-10-04 00:53:49下载
- 积分:1