CPLD下载线制作，内含电路图等，希望对大家有帮助

The program is used to establish communication with the pc through serial port. It utilses the inbuilt micro controller called as picoblaze for the processing for implementation on spartan 3E

saa7113_配置.SAA7113视频解码系列芯片的一种，8位彩色配置(saa7113_ configuration. SAA7113 video decoder chips in an 8-bit color configuration)

vhdl经典源代码――ps2接口设计，入门者必须掌握-vhdl classical source code-- ps2 interface design, beginners must master

基于Verilog+HDL设计CAN控制器,详细介绍各功能模块的设计。本论文的重点是CAN总线通信控制器的前端设计。即用Verilog HDL语言完成CAN协议的数据链路层的RTL级设计，实现其功能，并且能够在FPGA开发平台Quartos上通过仿真验证，证明其正确性(Verilog+ HDL-based design of CAN controller, detailed design of each functional module. This paper focuses on the CAN bus communication controller front-end design. Verilog HDL language that is used to complete the data link layer CAN protocol the RTL-level design, to achieve its function, and can be on the FPGA development platform Quartos by simulation to prove its correctness)

1.设计一个具有24进制计时、显示、整点报时、时间设置和闹钟功能的数字钟，要求时钟的最小分辨率时间为1s。2.多功能数字钟系统功能的具体描述如下：     计时：正常工作状态下，每日按24小时计时制计时并显示，蜂鸣器逢整点报时。     校时： 请点击左侧文件开始预览 ！预览只提供20%的代码片段，完整代码需下载后查看 加载中 侵权举报

基于FPGA的超声波测距，通过数码管显示距离(FPGA-based ultrasonic distance)

代码来源http://www.spacewire.co.uk/video.html，需要CRT显示ITU.656格式的视频的可以参考

在altera公司FPGA上自己构建了一个最简单的niosii sopc系统(Altera FPGA company on its own to build a simple system niosii sopc)

说明：  KMP算法的Verilog HDL实现，模式串从模块的外部输入，计算next函数，然后进行KMP匹配。有仿真。环境为Quartus II 8.0 Web Edition。(Verilog HDL implementation KMP algorithm, pattern string from the module' s external input, calculate next function, then KMP matching. A simulation. Environment for the Quartus II 8.0 Web Edition.)

This is a simple example of FIFO(first in and first out) module written in verilog code(This is a simple example of FIFO (first in and first out) module written in verilog code)