一种用于乘数的8x8的制备采用Verilog HDL语言

vhdl,双向移位寄存器，实现置数，左移及右移操作-vhdl, bi-directional shift register to achieve set the number of left and right shift operation

DDS信号发生器，能产生多种波形，正玄波，三角波，方波，频率可调，相位可调-DDS signal generator, can produce a variety of waveforms, are mysterious wave, triangle wave, square wave, frequency tunable, phase adjustable

Altera FIFO的多极级联，实现多个FIFO之间的数据传输。-Altera FIFO multi-polar cascading between multiple FIFO data transmission.

ssb的调制与解调，包括信号的产生、乘法器、加噪、BPF、解调等部分。(ssb modulation and demodulation, signal generation, multiplier, adding noise, BPF, demodulation section.)

quartus ii 中自动分配管脚的三种方法(quartus ii automatically assign pins are three ways)

2位并行加法器初学者必看初步了解FPGA-two count

利用AT89C51实现LCD日历电子钟源码-AT89C51 realization of the use of electronic LCD calendar clock source

说明：  彩条产生程序。。。。720p需添加74.25M时钟(colorbar generation. need 74.25mhz clock if 720p gen)

实现FDMA的仿真，3路输入信号，FFT输出(FDMA simulation input signal, FFT output)

电子秒表，FPGA实现,本科某课程设计，程序注释非常详细，(FPGA TIME-COUNTING)