DDS signal generator, can produce a variety of waveforms, are mysterious wave, t...

说明：  将外部的输入的6Mhz的信号分成为频率为153600hz的信号(The external input signal divided into 6Mhz 153600hz signal frequency)

载波同步的verilog代码，是新手学习同步的最佳选择，值得推荐。(Verilog code carrier synchronization, synchronization is the best choice for novices to learn, it is worth recommending.)

基于VHDL语言的CORDIC算法实现，用于计算sin(x),cos(x)等，实测可用(Based on VHDL CORDIC algorithm, used to calculate sin (x), cos (x), etc., the measured available)

用Verilog HDL编写的VGA显示驱动程序-Verilog HDL prepared with VGA display driver

针对32位MIPS微处理器中CLZ指令（对单个字高位连零进行计数）的实现电路，使用了类似于超前进位的逻辑结构。包含测试文档，以及Design Compile所用的环境和脚本。(The CLZ instruction counts the number of leading zeros in a word. The 32-bit word in the GPR rs is scanned from most-significant to least-significant bit.The number of leading zeros is counted and the result is written to the GPR rd. If all 32 bits are cleared in the GPR rs, the result written to the GPR rd is 32. )

SRAM的读写代码，对SRAM进行了乒乓操作，用VHDL语言进行设计，很有参考价值，甚至可以直接复制代码来进行自己的设计(SRAM read and write code, ping-pong operation carried out on the SRAM, using VHDL language design, of great reference value, or even directly copy the code to carry out their own designs)

SPI协议的VHDL/Verilog语言实现。(SPI agreement VHDL/Verilog language.)

该工程文件实现ARM系统中CPLD的逻辑工作，起到外围资源的逻辑地址译码功能-realization of the project document ARM system CPLD logic, external resources have address decoding logic function

通过数码管和单片机的组合 制作成的数码管时钟程序(Through the combination of digital control and made ​ ​ into a single-chip digital clock program)

用双端口ram实现异步fifo，采用格雷码，避免产生毛刺。-Using dual-port ram realize asynchronous fifo, the use of Gray code, avoiding the production of burr.