DDS signal generator, can produce a variety of waveforms, are mysterious wave, t...

说明：  Viterbi译码,IS-95中的1/2码率的卷积码(Viterbi decoding, IS-95 of 1/2 the rate Convolutional Codes)

FPGA锁相环实验： 顶层文件加底层IP文件构成 top中例化ip核pll(Experiment of Phase-Locked Loop Based on FPGA)

该代码使用 FSM 3 线串行 eeprom 与 fpga 的接口。它是由微芯片定义的接口。 该代码在串行 EPROM 中存储来自 ADC 的偏移量的错误。

SERDES资料，包括reliability_handbook,serdes_handbook,serdes_introduction(SERDES doc,include reliability_handbook,serdes_handbook,serdes_introduction)

系统介绍EDA技术的发展概述，相关概念，VHDL语言、MAX+PULS、QUARTUS的设计方法。-System overview of the development of EDA technology, related concepts, VHDL language, MAX+ PULS, QUARTUS design method.

说明：  CPU课程设计要求以FPGA开发平台为例，分析 CPU 设计的流程与仿真。 本次开发使用的硬件描述语言是 Verilog 语言，使用的指令系统是一个以 MIPS 指令集为子集的指令系统，共 22 条指令，所用的设计仿真软件Modelsim。(CPU curriculum design requires FPGA development platform as an example to analyze the process and Simulation of CPU design. The hardware description language used in this development is Verilog language, and the instruction system used is an instruction system with MIPS instruction set as a subset, with 22 instructions in total. The design simulation software Modelsim is used.)

上海大学 Verilog PPT 适合初学者看 推荐 -Shanghai University Verilog PPT look recommended for beginners

Multiplexer styles in VHDL

FPGA项目开发实战讲解 [李宪强编著][电子工业出版社][2015.04][248页].pdf(FPGA Project Development combat explain [Li Xingjiang ed] [Electronic Industry Press] [2015.04] [248] .pdf)

800 x 480 / inch lcd