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LCD1602测试程序
说明: 实现对LCD1602的Verilog HDL编程(the program for LCD1602 based on Verilog HDL)
- 2020-06-23 21:00:01下载
- 积分:1
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USB2.0的IP核(详细verilog源码和文档)
USB2.0的IP核开发.代码可以直接使用已经验证过(USB2.0 IP kernel development. Code can be used directly, has been verified)
- 2020-12-24 18:49:04下载
- 积分:1
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vhdl-cordic-atan-master
说明: Implementation of CORDIC atan block in VHDL
- 2019-05-14 16:51:26下载
- 积分:1
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comp
The red arrow showed the output became 8 when the measured temperature changed to 11°C. As shown by black arrow, the maximum output was 28. The program was run according to the proposed method.
- 2012-06-05 23:16:25下载
- 积分:1
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that I wrote four string and turn ISE code In xilinx Spartan3E debugging has bee...
这是我自己写的4位并转串ISE代码,在xilinx Spartan3E 上已经调试成功,拿出来与大家分享!-that I wrote four string and turn ISE code In xilinx Spartan3E debugging has been successful, with the show to share with you!
- 2022-02-14 20:17:51下载
- 积分:1
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Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0],...
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shift number. The shift range is 0 to 15.
6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it
shifts input data to left.
7. When the signal SIGN is high, the input data is a signed number and it shifts with
sign extension. However, the input data is an unsigned number if the signal SIGN
is low.
8. You can only use following gates in Table I and need to include the delay
information (Tplh, Tphl) in your design.
- 2022-04-13 06:40:15下载
- 积分:1
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用FPGA 是先键盘的程序,is good for you
用FPGA 是先键盘的程序,is good for you -FPGA is the first keyboard to use the procedure, is good for you
- 2023-08-22 22:30:03下载
- 积分:1
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FPGA_UART
用Verilog语言实现的FPGA UART独立收发模块
思路简单,代码简洁。在Lattice LFE3EA VERSA开发板上验证通过,编译器Lattice Diamond.
功能:串口收到数据后立即回传,此后每一秒串口数据+1再发送。(Using Verilog language independent of FPGA UART transceiver idea is simple, concise code. Development board in Lattice LFE3EA VERSA verified by the compiler Lattice Diamond. Features: Serial data is received immediately after the return, then every second serial port and then send the data+ 1.)
- 2011-10-03 13:18:56下载
- 积分:1
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FSK
频移键控FSK的Verilog实现,带测试文件,并在FPGA开发板上成功验证(Frequency Shift Keying FSK the Verilog implementation, with the test file, and successfully verified in FPGA development board)
- 2020-09-03 11:28:07下载
- 积分:1
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IIC-SOPC
SOPC系统的I2C代码 直接可用,可作为IP核用到自己的系统中(SOPC system I2C code directly available, can be used as an IP core in your system)
- 2010-10-22 09:51:13下载
- 积分:1