Altera FIFO的多极级联，实现多个FIFO之间的数据传输。

一个实用的uart协议模块，使用verilog 实现(A practical uart protocol modules, use verilog to achieve)

该程序是一个可完成订制化的SPI双向总线接口，时钟相位、极性，以及分频比全部可通过寄存器进行配置，已经在ISE下通过综合，占用资源少，强烈推荐 (The program is a complete custom of SPI bidirectional bus interface, clock phase, polarity, and the divider ratio can all be configured through the register, has been in the ISE through an integrated, small footprint, it is strongly recommended)

组合电路的设计8位加法器设计(ADD8.vhd)-Combinational Circuit Design 8-bit adder design (ADD8.vhd)

这是一个利用verilog语言编写的信号发生器的例子，值得参考(this is a code about signal generator by VIERILOG LANGUAGE!)

简易环形FIFO的设计、简单异步串行通信接口设计等-verilog

these files are written in verilog but i am uploading in text format

这是一些小代码的集合 希望能对大家有所帮助(This is a collection of some small code for all of us hope to be helpful)

利用两个半加器来组成的全加器，是简单的vhdl语言入门-The use of two and a half adder to form the full adder is a simple entry-vhdl language

其中两个项目自己做的：一个是雷达模拟跟踪，基于FPGA/CPLD的，里面包含了PCB和VHDL码，还有一个是SDIO的驱动程序（包括PCB原理图，SDIO协议方面的资料还有就是源码，这项目可用），还有一些嵌入式方面的资料，如TCP/IP协议栈的实现，FPGA的一些仿真实例(Two of the projects themselves to do: a tracking radar simulator is based on FPGA/CPLD)

FPGA AD数据采集模块，实现模拟信号到数字信号转换。(FPGA AD data acquisition module, the analog signal to digital signal conversion.)