2位并行加法器初学者必看初步了解FPGA

AHB master总线verilog实现(Implementation of AHB master bus Verilog)

用VHDL语言编写的AT24C02程序，并用数码管显示，本程序已经经过本人测试过，很好用-The AT24C02 is available VHDL language program, and use digital tube display, this procedure has been tested himself, very good to use--

说明：  关于usb调试相关测试 代码，用于测试和适配等(usb coding for testing , verigy, for studing usb and fpga)

图像处理的中值滤波器，使用verilog开发环境编程实现。(Verilog development environment programming median filter)

这是脉冲宽度调制技术的VHDL代码，包括一个比较器，正弦波发生器，锯齿波发生器，脉冲宽度调制器等。

altera嵌入式设计大赛文章，车载cots设计实现-Embedded Design Contest altera article, cots Car Design

说明：  fpga版本的数码管动态扫描程序，可供学习(FPGA version of the digital tube dynamic scanning program for learning)

基于fpga的多功能数字时钟的实现，已经编译过了，绝对可行-fpga-baseed clock

16位右移位寄存器 下面描述的是一个位宽为16位的右移位寄存器，实际具有环形移位的功能，是在右移位寄存器的基础上将最低位的输出端接到最高位的输入端构成的。其功能为当时钟上升沿到达时，输入信号的最低位移位到最高位，其余各位依次向右移动一位。(16-bit right shift register The following description is a right shift register with a bit width of 16 bits. It actually has the function of circular shift. It is based on the right shift register, which connects the lowest bit output terminal to the highest bit input terminal. Its function is that when the rising edge of the clock arrives, the lowest displacement of the input signal reaches the highest position, and the rest of you move one bit to the right in turn.)