这是一个基本的ARM7_Core 有基本功能 但不是太完善

USB接口控制器参考设计，xilinx提供的VHDL源代码-USB interface controller reference design for Xilinx VHDL source code

Am29LV160D数据基本知识手册，基本原理及工作方式。(Am29LV160D Data basic knowledge Manual, the basic principle and ways of working.)

FPGA经验总结：时序是设计出来的 我们在做详细设计的时候，对于一些信号的时序肯定会做一些调整的，但是这种时序的调整最多只能波及到本一级模块，而不能影响到整个设计。(FPGA Experience: Timing is designed to do the detailed design of our time, for some signal timing will certainly make some adjustments, but adjust this timing can only spread to up to this level of the module, but not affect the whole design.)

图像采集、存储控制verilog源代码(Image acquisition, storage, control of Verilog source code)

support for Coldfire m5441x processors.

说明：  libero soc工程，实现通过串口接收到单字节数据后并返回发送给上位机(Libero SOC project, which realizes receiving single byte data through serial port and sending it back to host computer)

数字滤波器的C语言实现，，包含高通、低通、带通滤波器 (The C language implementation of the digital filter, including the high-pass, low pass, band-pass filter)

说明：  FPGA 读写 SRAM 存储块，verilog代码(Read and write SRAM memory block and Verilog code in FPGA)

这是一个数字逻辑课程的电子表的实现，利用VHDL语言实现，初学者可以完全掌握，很有帮助。

正弦波VHDL语言~~~ ~~~ ~~~`-Sine wave VHDL language ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ `