modelsim的使用如何操作使用和安装如何安装

用verilog写的cpld的各种分频程序，希望大家指正，谢谢！-using Verilog cpld written by the various sub-frequency procedures in the hope that we stand corrected, thank you!

本文是Altera公司编写的dspbuilder的设计方法，但是是英文原版的(This article is prepared by Altera Corporation dspbuilder design method, but it is the original English edition of)

说明：  用VHDL语言设计一个校验器，用for loop实现8位数据的偶校验，(With a for loop to achieve 8-bit data parity)

74ls138组成16..4线编码器 经过本人验证(74ls138 composed of 16 .. 4 line encoder after I verify)

fpga正弦波发生函数，可用于自动生成rom文件(fpga sine wave generating function)

verilog实现ALU的源代码，并提供了一个详细的测试平台！-achieve ALU Verilog source code, and provide a detailed test platform!

VHDL fft 源程序，直接运行就可以，很好的一个程序-VHDL fft source code can be run directly, a very good program

this project is about FIR FIlter By VHdl codes in the ISE.

FPGA驱动VGA接口显示字符 -FPGA-driven interface VGA display characters

说明：  编码方式为213的Viterbi卷积码编码器和译码器的FPGA的实现，包含整个QuartusＩＩ的工程文件，解码方式为寄存器交换法(Encoding for the 213 convolutional code encoder and Viterbi decoder FPGA realization of the project file that contains the entire QuartusII, decoding method for the register exchange)