用verilog写的cpld的各种分频程序，希望大家指正，谢谢！

maxplus2为开发环境 vhdl编写的 键盘 程序-maxplus2 VHDL development environment for the preparation of the keyboard procedures

verilog ADPLL file with testbench

说明：  SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals in various formats. The cores connect using AXI-streams. Most configurations (resolution, framerate, colordepth, etc.) are set at compile-time using Verilog parameters. See svo_defines.vh for details on those parameters.

spartan6 里使用DDR3IP核，有教程以及源码(spartan6 with ddr3,source and tutorial)

misp顶层文件，verilog实现misp架构，并且支持modelsim仿真(Verilog implements MISP architecture and supports Modelsim simulation)

直接序列扩频通信系统： 包含： 信源、扰码、交织、直扩、BPSK调制、解调、相关、解交织、解扰 请点击左侧文件开始预览 ！预览只提供20%的代码片段，完整代码需下载后查看 加载中 侵权举报

FM收音机的解码及控制器VHDL语言实现，Xilinx提供的．别谢我．-FM radio decoder and controller VHDL, Xilinx provide. I thank other.

verilog实现UART收发功能，硬件平台为spartan 6，软件平台为ise14.7(verilog implement UART rx and tx function)

51单片机测试程序，ＩＣ:UC1676,4线串口(51 MCU test program, IC:UC1676 4-LINE, SPI INTERFACE)

基于fpga的电子血压计。pdf文档，好用，内容清楚简单，转载而来(Electronic sphygmomanometer based on fpga)