在QuartusII下进行编译和仿真的时候,会出现一堆warning,有的可以忽略,有的却需要注意...

Synchronous Resets? Asynchronous Resets?I am so confused!How will I ever know which to use? 复位信号的论文-Synchronous Resets Asynchronous Resets I am so confused! How will I ever know which to use Minute Signal-paper

说明：  通过MATLAB产生单脉冲信号的数据，存储下来作为verilog代码实现的DDS的数据源，用于验证DA数据的ddio的调试是否有问题。(The data of monopulse signal generated by MATLAB is stored as the data source of DDS implemented by Verilog code to verify whether the ddio debugging of DA data is problematic.)

设计一个简单的FIR滤波器，并按要求确定滤波器的系统函数。(Design a simple FIR filter, and determine the filter according to the requirement of system function.)

在开发板EGO1上实现赛车游戏,语言为verilog，内含bits文件(racing game in verilog)

Xilinx,Altera,ARM,AVR,S52,Lattice等系列FPGA的下载线电路图和PCB(Xilinx, Altera, ARM, AVR, S52, Lattice series FPGA download cable circuit diagram and PCB)

source vhdl code of D flipflop logic

在Altera的FPGA开发板上运行第一个FPGA程序，以后我还会陆续发布这方面的代码-In Altera

程序用VHDL实现： 利用一秒定时测量频率 并且显示，范围0~-VHDL 0~

FPGA AD数据采集模块，实现模拟信号到数字信号转换。(FPGA AD data acquisition module, the analog signal to digital signal conversion.)

    本资源详细的设计了一个FIFO的用法，将数据从ROM中读取送到FIFO缓存中然后RAM从FIFO缓存中读取数据存到内存中，改程序可以很好的学习三者之间的关系