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chaotic_1d
说明: 一维超混沌随机数的生成verilg,还有testbench仿真激励,modelsim的仿真工程。(The generation of one-dimensional hyperchaotic random number verilg, testbench simulation stimulation and Modelsim simulation engineering.)
- 2020-05-11 12:45:42下载
- 积分:1
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"digital circuit EDA portal
《数字电路EDA入门-VHDL程序实例》---交通灯程序例子-"digital circuit EDA portal-VHDL program examples"-- traffic lights procedures example
- 2022-02-19 21:55:09下载
- 积分:1
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vivado2018+IPs
说明: Xilinx Vivado 2018 License File
- 2021-01-19 22:08:41下载
- 积分:1
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sopcAD7352nios
基于sopc的7352的ad模块的nios软核多通道编写,verilog 写的(The sopc 7352 AD module nios soft core multichannel write. Rar
)
- 2012-11-03 21:37:42下载
- 积分:1
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VHDL的您的信息的一个游戏程序的源代码,我希望那些在…
一个游戏程序vhdl源码,供大家参考,希望有兴趣的人下载-VHDL source code of a game program for your information, I hope those who are interested in downloading
- 2022-03-19 17:54:49下载
- 积分:1
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Temperature measurement
Using LabVIEW FPGA, Spartan3E, PMODTMP
Temperature measurement
Using LabVIEW FPGA, Spartan3E, PMODTMP
- 2022-03-05 00:22:10下载
- 积分:1
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matlab
里面包含了三段代码,主要是用matlab产生高斯随机信号以及高斯白噪声和色噪声,然后计算其数字特征及对这些信号进行频谱分析和功率谱分析,里面还有关于低通滤波器的设计的简单说明(Which contains three sections of code using matlab Gaussian random signals and white Gaussian noise and color noise, and then to calculate the numerical characteristics and spectral analysis and power spectral analysis of these signals, there is also the low-pass filter design BRIEF DESCRIPTION OF)
- 2020-09-22 15:17:51下载
- 积分:1
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课程设计-数字钟
说明: 具有计时 设置时间 闹钟 秒表 功能的数字钟设计 外设矩阵键盘(Digital clock design peripheral matrix keyboard with the function of timing setting time alarm clock stopwatch)
- 2020-05-18 17:11:07下载
- 积分:1
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Altera in the official line on the SOPC custom component (PWM) of the examples a...
Altera官网上关于SOPC中自定义组件(PWM)的实例,官网上现在没了。。可很多书上都在用-Altera in the official line on the SOPC custom component (PWM) of the examples are not the official line. . Can be a lot of books are in use. . .
- 2022-02-04 13:32:48下载
- 积分:1
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Based on the state of the optical encoder Figure 4 multiplier vhdl procedure, en...
基于状态图的光电编码器4倍频vhdl程序,输入相位差90度的两相,输出倍频和方向信号-Based on the state of the optical encoder Figure 4 multiplier vhdl procedure, enter a 90-degree phase difference of two-phase, frequency and direction of the output signal
- 2022-03-17 02:46:02下载
- 积分:1