并行通信代码（调试通过）

说明：  FPGA实现基带成型滤波器，升余弦滚降系数，多进制调制(FPGA)

The program is used to establish communication with the pc through serial port. It utilses the inbuilt micro controller called as picoblaze for the processing for implementation on spartan 3E

verilog 实现的FFT 流水线操作，速度能达到200M(verilog pipelining the FFT implementation, the speed can reach 200M)

vhdl状态机设计,文件简单详细易懂，可以使用在交通灯，文件配置等系统上。(vhdl state machine design, simple, detailed and easy to understand, you can use the traffic light system file configuration file.)

verilog HDL编写的出租车计费系统-verilog HDL prepared Taxi Accounting System

stepper motor module on spartan 6 and 24MHz clock fequency

libero soc工程，实现通过串口接收到单字节数据后并返回发送给上位机(Libero SOC project, which realizes receiving single byte data through serial port and sending it back to host computer)

自编的64B/66B解码程序，做毕业设计的时候写的。(The decoding process 64B/66B , written when i am in the school。)

VHDL参考例程--日如DAC0832接口电路程序-VHDL reference routines- on procedures such as the DAC0832 Interface Circuit

用verilog写的卷积码的编码程序以及viterbi译码程序(Use verilog write convolution code coding procedures and viterbi decoding program)