并行通信代码（调试通过）

UC1701串行编程例子，是一个很好的控制ＬＣＤ模块的Ｃ语言串行编程(UC1701 serial program)

verilog编写实用多功能电子表-Verilog prepared practical multi-function electronic Table

基于FPGA开发的11阶半带升余弦FIR滤波器，用在阅读器基带滤波时的抽取滤波器使用，采用verilog语言实现。(Raised cosine FIR filter based FPGA development 11 order of half-band decimation filter used in reader baseband filtering, using verilog language implementation.)

FPGA中针对Biss通讯协议解码VHDL语言源码(FPGA communication protocols against BiSS source decoder VHDL language)

GMSK的调制解调，理理想信道，画出其功率谱。 (GMSK modulation and demodulation, management ideal channel, to draw its power spectrum.)

说明：  quartusii软件仿真实验代码 双二选一(quartusii software simulation code for a pair of two elections)

说明：  浙江大学计算机组成实验12指令扩展多周期CPU实现(The implementation of 12 instruction extended multi cycle CPU in Computer Composition Experiment of Zhejiang University)

DDR2 SDRAM 控制器的FPGA实现-DDR2 SDRAM controller FPGA to achieve

采用verilog实现的有限域GF(28)弱对偶基乘法器，本原多项式: p(x) = x^8 + x^4 + x^3 + x^2 + 1 ，多项式基: {1, a^1, a^2, a^3, a^4, a^5, a^6, a^7}，弱对偶基: {1+a^2, a^1, 1, a^7, a^6, a^5, a^4, a^3+a^7}(Verilog achieved using the finite field GF (28) weak dual basis multiplier)

用VHDL写的运动计时表程序，用Modelsim仿真已经通过，帖出来与大家分享。-write VHDL campaign time table program, Modelsim simulation has been passed, Tie up share with you.