并行通信代码（调试通过）

此代码完成了流水线CPU的设计。其中有ALU，控制模块，UART等verilog代码。(This code completes the design of pipelined CPU)

这个是vhdl中很常见的jk filpflop的文件只用于很小数位的变化 其中的jk文件是up down运算都符合的(This is a very common vhdl jk filpflop file is only used for very small changes in a digital file which jk is up down operations are met)

quartusii 三分频电路，大家帮参考一下，有什么问题-one-third of quartusii frequency circuit, refer to U.S. help, have any problem

60进制计数器,（由一六进制和十进制连线组成）(60 binary counter (hexadecimal and decimal by a connection form))

我的项目执行 filtrage 和抽取使用多相分解，在这种情况下，抽取因子被带到 5，所以筛选器由 5 集团过滤器和每个 oprates 在频率采样除以 5

ALTERA 的关于对SDRAM控制器操作的verilog相关程序，很不错绝对值得借鉴。-ALTERA on the operation of the SDRAM controller Verilog procedures, it is definitely worth a good draw.

这个是一个基于FPGA的SDRAM控制器系统，实现对SDRAM的读写操作，用来实现时序的控制-This is an FPGA-based SDRAM controller system, the read and write operations to SDRAM to achieve the control of timing

按键控制LED流水灯；按键1按下前8个灯从左到右依次点亮，按键2按下中间前8个灯从左到右依次点亮，按键3按下所有灯全亮(Water control button LED lights sequentially lit buttons the eight lights left to right 1 Press button 2 press from left to right is lit in the middle eight lights, key 3 Press All full bright light)

fpga clock 设计，资料较好，供大家参考，非商用目的哦-fpga clock design, the information is better, for your reference, non-commercial purposes Oh

有限状态机工作原理、设计方法、步骤等精要说明(Finite state machine working principle, design method, such as Essentials of steps to explain)