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avnet_edk12_4_xbd_files
安富利SP605开发板ISE12.4版本的XBD文件,里面包括了开发板所有的接口,包括硬件和软件设计(Avnet SP605 development board ISE12.4 version XBD file, which includes the development board all interfaces, including hardware and software design)
- 2014-04-20 21:56:05下载
- 积分:1
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功率门控IEEE论文可为IP核的实现充分利用
ieee paper on power gating and can be use full for implementing on ip core
- 2022-02-03 18:58:04下载
- 积分:1
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三角波的产生
这是源代码,该代码为三角波的一代,在 VHDL 写。欢迎下载。谢谢你的支持。
- 2022-08-03 08:08:41下载
- 积分:1
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步进电机
此代码是用于旋转一个步进电机所需的方向。
- 2022-10-22 10:05:04下载
- 积分:1
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VHDL_count 从 0 到 9 4 7 段 LED 显示器 (đếm 0 đến 9 hiển 施耐 4 带领 7 đoạn)
VHDL_count 从 0 到 9 4 7 段 LED 显示器 (đếm 0 đến 9 hiển 施耐 4 带领 7 đoạn)
- 2022-01-20 23:11:51下载
- 积分:1
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Verilog 编写的IP核,512K的16位SRAM
Verilog 编写的IP核,512K的16位SRAM-Written in Verilog IP core, 512K 16-bit SRAM
- 2023-01-13 23:15:04下载
- 积分:1
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ozgul2013
说明: Digital pre-distortion (DPD) is an advanced digital
signal-processing technique that mitigates the effects of power
amplifier (PA) nonlinearity in wireless transmitters. DPD plays
a key role in providing efficient radio digital front-end (DFE)
solutions for 3G/4G basestations and beyond. Modern FPGAs
are a promising target platform for the implementation of flexible
wireless DFE solutions, including DPD.
- 2019-01-05 18:20:30下载
- 积分:1
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cordic implementation in vhdl&c
cordic implementation in vhdl&c
- 2022-10-31 01:55:03下载
- 积分:1
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crc8
8位crc的verilog设计 通过仿真综合验证并已应用在工程里面
(verilog of 8bit error checkout )
- 2021-03-01 11:09:34下载
- 积分:1
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SPI的verilog代码的可编程时钟
SPI Verilog code with programmable clock
- 2022-10-30 18:55:03下载
- 积分:1