并行通信代码（调试通过）

Two-Dimensional Rank Order Filter Author: Gabor Szedo

做EDA的，就不用介绍这个文件了吧，IEEE1364标准（开放）。-done, would not have introduced the document on the bar, IEEE1364 standard (open).

verilog，4、5分频器，5分频器占空比3：2-Verilog, 4,5 dividers, five dividers ratio of 3:2

高性能FPGA应用领域及其研究，FPGA的开发流程-High-performance FPGA applications and research, FPGA development flow

6264是一种8K×8的静态存储器.SRAM 的典型芯片有2KB 的6116、8KB 的6264 以及32KB的62256,其中6264 芯片应用最为广泛.(6264 is the 62256 typical chip SRAM.SRAM a 8K* 8 with 2KB 6116, 8KB 6264 and 32KB 6264 chip, which is most widely used. )

fpga串口的接收程序基于verilog语言拿走不用谢。(The receiving program of FPGA serial port is based on Verilog language.)

AD7606采集代码，用于verilog 驱动 AD7606 adc SPI 串口方式(AD7606 acquisition code, used for Verilog drive AD7606 ADC SPI serial mode)

CAN总线的数据采集，FPGA到USB。verilog hdl语言。(CAN bus data acquisition, FPGA to the USB. verilog hdl language.)

交通灯的控制，分主干道和从路交通灯，主路优先，正常情况下，绿灯60s，红灯30S，黄灯5S(Traffic light control)

基于COMTEX-M3的IEEE1588,irigB对时的源程序，包括GPS对时程序，并将对时的结果写入FPGA中(Based COMTEX-M3 of IEEE1588, irigB on time source, including GPS for the program, and writes the results when the FPGA)