vhdl code for multiplexer and detemines how multiplexer works

说明：  NAND FLASH的多个仿真模型，可以用于接口设计的测试(NAND FLASH multiple simulation model that can be used for the test interface design)

PLD与8051接口的参考设计 Xilinx提供的verilog源代码-PLD 8051 interface with the Xilinx Reference Design for the Verilog source code

FSK编码器和译码器,有需要的朋友可以看看！(FSK encoder and decoder, there is a need friends can see!)

本设计是基于EP4CE15F17C8N和12864液晶的频率计程序(The design is based EP4CE15F17C8N and 12864 LCD frequency meter program)

基于FPGA的VGA控制器，可在屏幕显示彩色条纹(A vga controller based on FPGA)

基于FPGA的 温度传感器 DS18B20接口设计-FPGA DS18B20

un controller pi par le langage VHDL xilinx ise design 13.2

VGA显示程序VHDL版本，适用于ALTERA的CPLD(VGA display program applies ALTERA CPLD)

人的移动的跟踪，VERILOG实现，能跟踪人的画面移动(Tracking the movement of people, VERILOG realize that can track the person)

说明：  熟悉IIC协议总线协议，采用IIC总线对图像采集传感器寄存器进行配置，并转换为RGB565格式。 利用异步FIFO完成从摄像头输出端到SDRAM 和SDRAM 到VGA 接口各跨时钟域信号的传输和处理。 利用 SDRAM 接口模块的设计，实现了刷新、读写等操作；为提高SDRAM 的读写带宽，均采用突发连续读写数据方式；并采用乒乓操作实现 CMOS 摄像头与VGA的帧率匹配。 利用双线性插值方法实现对图像640×480到1024×768的放大操作。 完成VGA显示接口设计。(Familiar with IIC protocol bus protocol, IIC bus is used to configure the register of image acquisition sensor and convert it into RGB565 format. Asynchronous FIFO is used to transmit and process signals across clock domain from camera output to SDRAM and SDRAM to VGA interface. With the design of SDRAM interface module, refresh, read and write operations are realized. In order to improve the read and write bandwidth of SDRAM, burst continuous read and write data mode is adopted, and table tennis operation is used to achieve frame rate matching between CMOS camera and VGA. The bilinear interpolation method is used to enlarge the image from 640*480 to 1024*768. Complete the VGA display interface design.)