海力士公司8M字节的SDR SDRAM实现Verilog仿真语言。

VCP201_CODE is a FPGA source code.

4选1数据选择器，有使能端控制，4个数据输入，2个地址端，1个输出(4 1 data selector, enable end control, four data inputs, two addresses end, an output)

hilbert 变换的vhdl源代码，来源于网上，本人也做过简单的8抽头的，但这个的算法还没搞懂，希望懂行的下载了研究一下，给个中文的简单的说明！(hilbert transform VHDL source code from the Internet, I have been a simple 8-tap, but even before they get to know this algorithm, I hope knowledgeable downloaded to look for a simple description of the Chinese!)

GFHGFHGFH DFHFDHD GHDHFDHHFD DFHFDHDF

AD conversion using LTC1298

A design on a DE270 FPGA with the use of CCD: a camera DC2 and a TRDB LTM after reading from the SRAM.

使用verilog hdl语言编程正弦波信号，能仿真出结果(Can use verilog HDL language programming sine wave signal, the simulation results )

hdmi 视频编解码输入输出模块，verilog实现(hdmi encoder and decoder in verilog.)

本书是一本Verilog语言设计和综合手册,对学习Verilog语言有很大作用,值得阅读.

数字信号除了的FPGA实现的Verilog源代码，之前发过一份是VHDL，各有所需吧，需要的看看吧(Digital signal in addition to the realization of the FPGA Verilog source code, send before a is VHDL, each have need it, need to look at it )