海力士公司8M字节的SDR SDRAM实现Verilog仿真语言。

DDS中的正余弦生成，初始相位相差90度，可自行改变输出频率(Cosine generation of DDS, the initial phase difference of 90 degrees, the output frequency can be changed on their own)

滤波器 Generaic FIR Filter(Generaic FIR Filter)

AES算法部分模块行位移列变换以及主题程序加密解密(AES algorithm transforms part of the module rows and columns relating to the displacement of encryption and decryption program)

morris mano basic vhdl code in ise

fpga debounce filter code in vhdl

FPGA设计中的时序分析及异步设计注意事项 (FPGA design timing analysis and design considerations for asynchronous)

基于FPGA的Verilog语言实现的六十进制计数器(FPGA-based Verilog language implementation of six decimal counter)

4. If a modified source code is distributed, the original unmodified -- source code must also be included (or a link to the Free IP web -- site). In the modified source code there must be clear -- identification of the modified version.-4. If a modified source code is distributed, the original unmodified-- source code must also be included (or a link to the Free IP web-- site). In the modified source code there must be clear-- identification of the modified version.

一位LED显示的VHDL程序，挺简单的，买的开发板里面带的-An LED display of the VHDL program, quite simply, to buy development board inside the zone

  设计一个具有较高安全性和较低成本的通用电子密码锁，其具体功能要求如下:  (1) 数码输入：每按下一个数字键：就输入一个数值，并在显示器上的最右方显示出该数值，同时将先前输入的数据依序左移一个数字位臵 (2) 数码清除：按下此键可清除前面所有的输入值，清除成为“0000”。 (3) 密码更改：按下此键时会将目前的数字设定成新的密码。 (4) 激活电锁：按下此键可将密码锁上锁。 (5) 解除电锁：按下此键会检查输入的密码是否正确，密码正确即开锁。