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10_100fsrb.pdf
Ethernet Media Access Controller
- 2014-04-30 19:56:17下载
- 积分:1
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VerilogHDL_DC_Motor_control
采用Verilog HDL语言编写的直流电动机控制系统,主要完成直流电动机的速度控制,典型的三闭环(位置、转速和电流反馈)直流电机控制系统,对控制类相关的学习者价值很高(Using Verilog HDL language of the DC motor control system, mainly the completion of DC motor speed control, a typical three-loop (position, speed and current feedback) DC motor control system for control-type high-value related to the learner)
- 2008-01-10 23:34:29下载
- 积分:1
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ug835-vivado-tcl-commands
说明: Vivado是Xilinx最新的FPGA设计工具,支持7系列以后的FPGA及Zynq 7000的开发。与之前的ISE设计套件相比,Vivado可以说是全新设计的。无论从界面、设置、算法,还是从对使用者思路的要求,都是全新的。看在Vivado上,Tcl已经成为唯一支持的脚本,此文件是vivado是tcl命令的集合。(Vivado is Xilinx's latest FPGA design tool that supports development of FPGAs and Zynq 7000s in the 7 series and beyond. Compared with the previous ISE design suite, Vivado can be said that the new design. No matter from the interface, settings, algorithms, or from the user ideas, are new. Look at Vivado, Tcl has become the only supported script, this file is vivado tcl command collection.)
- 2020-10-26 22:50:00下载
- 积分:1
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shumagua
通过数码管和单片机的组合 制作成的数码管时钟程序(Through the combination of digital control and made into a single-chip digital clock program)
- 2013-10-27 12:30:04下载
- 积分:1
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SD-Host-Controller-master
说明: sd卡的verilog代码,包含一些sd卡例程(SD card Verilog code, including some SD card routines)
- 2021-04-29 13:48:42下载
- 积分:1
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crc16_8
modbus通讯必须的校验码生成器,可以直接使用(modbus crc16/8 free use)
- 2020-10-22 10:47:23下载
- 积分:1
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yunchengxu
说明: 内附几十种小程序,有状态机、比较器、波形发生器、乘法器、加法器、步进电机控制器等,希望大家能用的上。(Containing dozens of small programs, for reference,This is about FPGA,a tool ,we can study,but in ourselves.)
- 2010-04-29 16:00:25下载
- 积分:1
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ht66f0185-1
小家电常用芯片HT66F0185的UART 使用例子,已在产品使用(Small appliances commonly use UART chip HT66F0185 of example, has been used in products)
- 2020-10-09 16:27:34下载
- 积分:1
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test2
说明: 试用Verilog HDL语言,设计十进制计数器,将计数过程用一个数码管进行显示(0~9)。要求首先使用Modelsim软件进行功能仿真,然后使用Quartus软件综合,并下载到开发板进行电路功能测试。(Using Verilog HDL language, a decimal counter is designed. The counting process is displayed by a digital tube (0 ~ 9). It is required to first use Modelsim software for functional simulation, then use quartus software for synthesis, and download to the development board for circuit functional test.)
- 2020-05-17 11:07:28下载
- 积分:1
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lab_instructions3
The objective of the labs today is to give you a basic understanding of FPGA design and
enough experience to begin your own FPGA design with the ISE 10.1 tools and the
Xilinx Spartan-3A DSP 1800A Starter Kit.
- 2010-12-31 17:16:42下载
- 积分:1