海力士公司8M字节的SDR SDRAM实现Verilog仿真语言。

利用cordic实现直角坐标与极坐标的转换，用vhdl实现-use cordic achieve very Cartesian coordinates with the conversion, with vhdl achieve

本白皮书探讨了在PCI Express的因素 技术可能会影响性能。它还 提供指导如何估算 的系统性能。(This white paper explores the factors in PCI Express technology may affect performance. It also provides guidance on how to estimate the system performance.)

PLD与8051接口的参考设计 Xilinx提供的verilog源代码-PLD 8051 interface with the Xilinx Reference Design for the Verilog source code

设计制作一个可容纳4组参赛者的数字智力抢答器，每组设置一个抢答按键； 电路具有一第一抢答信号的鉴别和锁存的功能。在主持人将系统复位并发出抢答指令后，若参加者按抢答键，则该组指示灯亮并用组别显示抢答者的组别。此时，电路具有自锁功能，使别组的抢答开关不起作用。 设置计分电路。每组在开始时预置成6分，抢答后主持人计分，答对一次加1分。(The design can accommodate a the Entrants digital intellectual Responder, each set answer in a key circuit has a first answer in the signal to identify and latch functions. Host to the system reset and sent the answer in instruction, participants answer in key, the group of the group light and display the answer in the group. At this point, the circuit has a self-locking function does not work in other groups to answer switch. Set Scoring circuit. Preset six points each at the beginning of the answer in scoring after the host, answer time, add 1 point.)

用CPLD驱动扬声器实现音乐的播放，程序是用VERILOG写的，-CPLD driver speakers with music player, the program is written in VERILOG,

静态功耗减少使用多 thershld< 跨度 style="font-size:12.0pt;line-height:115%;font-family:"color:#222222;background:white ；"> 多阈值 CMOStransistors 是非常手术滴备用泄漏功率 duringwhen IC 为较长时间内不活动。最近，功率 gatingscheme 提出了维护多个关闭电源模式和减小电极电源甚至短的不活跃时期。但是，这种系统能进行从高灵敏度对工艺参数变化。我们建议新浇注逻辑开关，是容错过程和 reducepower 在任何数字电路。预计的提案需要很少的金额项目努力和妥协降低功耗较大和较低的面积开销比早些时候的方法。此外，它可以团结生存系统 toproposition 额外的静态功耗减少方面受益。考试广泛娱乐的成果证明成功的拟议的设计

介绍了基于Altera 公司的CPLD 芯片FL EX10 K,以及利用VHDL 语言实现多位二进 制码转换成8421BCD 码的原理、设计思路和软件实现。-Introduction based on Altera

Everspin SPI MRAM chipset(MR25H10,MR25H40,MR25H256)

和picoblaze完全兼容的mcu ip core-And PicoBlaze fully compatible mcu ip core

RS(255,223)编解码算法。verilogHDL代码实现，在XILINX的芯片上得到验证。不包含任何IP核，方便移植到任何FPGA芯片。(RS (255223) encoding and decoding algorithm. VerilogHDL code to achieve, in the XILINX chip to be verified. Does not contain any IP core, easy to transplant to any FPGA chip.)