CCSDS预测编码

使用verilog语言描述的二阶巴特沃斯IIR滤波器，程序中有参数说明，已经运行通过(Using verilog language to describe the second-order Butterworth IIR filter, the program has parameter description has been run through)

axi_lite_user官方样例，精简功能，适用于zynq系列axi总线(Axi_lite_user official sample, streamline function, apply to zynq series Axi bus)

介绍了硬件语言的仿真软件modelsimse的操作是使用方法，可以为入门的参考资料-Introduction of the hardware language modelsimse operation simulation software is to use the method of reference for the entry

一些verilo的经典实例，非常适合初学者(verilo of the classic examples, for beginners)

vhdl programming from beginner level

uart_tr 异步串口通信主机 使用verilog HDL语言编写(uart_tr the host of the uart )

自己用verilog编写的urisc程序，调试成功，压缩包里有仿真图像，值得学习参考。(Written in verilog urisc program debugging, simulation image compression bag, worth learning reference.)

说明：  altera发布的开源8b10b源代码，vhdl语言描述(altera released the source code open source 8b10b, vhdl language description)

基于FPGA编写的verilog代码，在xilinx上仿真实现FFT变换(FPGA-based verilog code written in xilinx FFT transform Simulation)

MATLAB to HDL Code conversion