Turbo Decoder Release 0.3

Toplevel VHDL Structural model of a system containing 8051 -Toplevel VHDL Structural model of a system containing 8051

ldpc译码算法的matlab实现，码长960，码率1/2,完全模拟fpga硬件实现语言，量化处理。(ldpc decoding using matalb,code length 960,code rate 1/2)

verilog 编写的ldpc编码，含有两个文件(LDPC written by Verilog)

2011年全国大学生电子设计竞赛E题“简易数字信号传输性能分析仪”fpga的控制代码，verilog编写；包括了M序列及同步时钟的提取等所有程序。(2011 National Undergraduate Electronic Design Contest E title "Simple digital signal transmission performance analyzer" fpga control code, verilog prepared including the M-sequence and synchronous clock extraction and all other programs.)

雷达基本恒虚警处理，CA-CFAR(单元平均恒虚警处理),OS-CFAR（有序类恒虚警处理）,SO-CFAR（选小类恒虚警处理），(radar basic constant alarm operation,obtaining os-cfar,so-cfar,os-cfar,ca-cfar)

通过matlab对于声音进行处理，实现FFT，均值，方差，中值滤波，自相关分析，白噪声等处理(Matlab sound processing, FFT, mean, variance, median filtering, autocorrelation analysis, white noise and processing)

control stepper motor by fpga card with vhdl program

OMAP5912 UART的测试程序 包括头文件 源文件等。(OMAP5912 UART program test)

说明：  ZEDBOARD的管脚分配图和约束文件，包括PCB图和xdc文件(Pin assignment of ZEDBOARD)

fpga 设计全攻略，很好的fpga入门提高资料(the fpga design Raiders, good fpga the Getting Started improve data)