VHDL Digital Full ADDER Logic Program

用verilog编写的全数字锁相环，包括鉴相器，模K计数器，加减脉冲模块和分频模块，都经过验证(verilog based digital phase lock loop design, including phase detector,mode K counter, increment/decrement counter and frequency divider )

说明：  交通灯的控制，分主干道和从路交通灯，主路优先，正常情况下，绿灯60s，红灯30S，黄灯5S(Traffic light control)

HDL example source code 2/5 dff_en

actel公司用于1553总线的1553BRT-EBR核心代码 包括文档和代码非常有用(Actel company for the 1553 bus 1553BRT-EBR core code, including documentation and code is very useful)

verilog语言编写的jtag（边界扫描模块），初学的时候可以看看(verilog language jtag (boundary scan module), a novice when you can look)

结合XILINXCPLD所做的模拟RS232通信verilog源程序-XILINXCPLD combine the simulation RS232 communication Verilog source

图像采集、存储控制verilog源代码，fpga控制SAA1117,采集数据存储到sram，仿真编译测试都能通过(Image acquisition, storage, control verilog source code, fpga control SAA1117, collecting data to sram, simulation tests can be compiled by)

FPGA中针对Biss通讯协议解码VHDL语言源码(FPGA communication protocols against BiSS source decoder VHDL language)

FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation

说明：  16点verilog FFT，可供参考学习使用(16 points Verilog FFT can be used for reference)