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DDR_SDRAM_verilog
说明: DDR(双速率)SDRAM控制器参考设计verilog代码,可以直接用的,很好的(DDR (double rate) SDRAM controller reference design Verilog code, can be directly used, very good)
- 2021-03-13 16:39:24下载
- 积分:1
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LMP
利用LMP的20bit counter,比自带的cout进位要快的多。已经同错综合和时序仿真。-LMP
- 2022-01-25 18:35:46下载
- 积分:1
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用verilog编写的乒乓球游戏,内带ps2,VGA驱动,下载到spantan3开发板上即可使用(原创)...
用verilog编写的乒乓球游戏,内带ps2,VGA驱动,下载到spantan3开发板上即可使用(原创)-Prepared using Verilog table tennis game, with band ps2, VGA driver, download to spantan3 development board to use (original)
- 2023-07-23 17:15:04下载
- 积分:1
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soft for changing Verilog code to c++ code ,c code
将Verilog代码转换成C++代码的软件,C源代码。-soft for changing Verilog code to c++ code ,c code
- 2022-01-24 14:30:24下载
- 积分:1
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dac9747
主要完成ADI公司的DAC(数字-模拟转换器)AD9747的SPI接口及寄存器配置(Mainly to complete ADI' s DAC (digital- analog converter) SPI interface to configure the AD9747 and the register of)
- 2014-06-03 11:00:43下载
- 积分:1
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VHDL_PWM
FPGA,用VHDL语言产生可调的PWM波(FPGA, VHDL language adjustable PWM wave)
- 2020-12-20 21:29:09下载
- 积分:1
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四进制计数器模块,使用VHDL语言编写,在ISE8.1中经过测试的模型...
四进制计数器模块,使用VHDL语言编写,在ISE8.1中经过测试的模型-quaternary counter module, the use of VHDL language, in which ISE8.1 tested model
- 2022-02-06 20:22:16下载
- 积分:1
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循环码的verilog编码程序
(7,4)循环码的verilog编码程序,(7,4)循环码的verilog译码程序((7,4) cyclic code Verilog coding procedures, (7,4) cyclic code the verilog decoding procedure)
- 2020-06-27 02:00:02下载
- 积分:1
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the major digital TV front
主要完成数字电视前端信号处理和缓冲作用的verilog源代码,可以直接使用 -the major digital TV front-end signal processing and buffer the Verilog source code can be used directly
- 2022-04-09 13:15:30下载
- 积分:1
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a program which divides the clock by 3
a program which divides the clock by 3
- 2022-01-25 14:21:33下载
- 积分:1