NIOS II IDE 编程， FLASH测试程序，仅供参考。

High-Speed Data Serialization and Deserialization(840 Mb/s LVDS) for xilinx fpga

在FPGA上编写的通过SPI总线配置外部DAC芯片DAC5686的程序，通过板级调试，验证可用。程序通过状态机实现，将需要配置的寄存器值转为SPI总线的数据格式发送出去。 (Configure external DAC chip DAC5686 via SPI bus program on FPGA written by board-level debugging, verification is available. Program through the state machine, you will need to configure the register values 椠渀琀漀 SPI bus data format sent.)

系统介绍EDA技术的发展概述，相关概念，VHDL语言、MAX+PULS、QUARTUS的设计方法。-System overview of the development of EDA technology, related concepts, VHDL language, MAX+ PULS, QUARTUS design method.

Verilog 下脉冲发生器的源代码，可用于模拟三相交流电过零点，主要用于调试一些类似SVC（无功补偿）控制器的一些算法-Pulse generator under the Verilog source code, can be used to simulate three-phase alternating current zero-crossing point, mainly for debugging similar SVC (reactive power compensation) controller of a number of algorithms

program for half subtractor.

本例为ADC0809接口电路VHDL程序原代码-The ADC0809 Interface Circuit Example for VHDL program source code

Sample behavioral waveforms for design file sin_rom.vThe following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design sin_rom.v. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 3F0, 3F1, 3F2, 3F3, ...). The design sin_rom.v has one read port. The read port has 1024 words of 10 bits each. The output of the read port is unregistered. Fig. 1 : Wave showing read operation. The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until

3g-sdi驱动器，用于全高清视频FPGA解决方案(3g-sdi driver)

(Springer Series in Advanced Microelectronics 51) Ayan Palchaudhuri, Rajat Subhra Chakraborty (auth.)-High Performance Integer Arithmetic Circuit Design on FPGA_ Architecture, Implementation and Desig

多功能数字钟，1、采用24小时制：时、分、秒计时、显示。 2、具有手动校准功能：分为时校准、分校准。 3、秒复位 4、闹钟功能 5、整点报时：仿中央人民广播电台整点报时信号