NIOS II IDE 编程， FLASH测试程序，仅供参考。

code for kcpcm3 : Describes the working of KCPCM3 embedded in picoblaze xilinx-code for kcpcm3 : Describes the working of KCPCM3 embedded in picoblaze xilinx

1024点FFT快速傅立叶变换，包含说明文档和VHDL源代码，16位输入/输出，带DMA功能，xilinx的ip-1024-point FFT fast Fourier transform, and includes documentation, VHDL source code, 16 input/output, with DMA function, the ip xilinx

xilinx verilog FPGA驱动AD9613 数据采集DEMO程序(Xilinx Verilog FPGA drives AD9613 data acquisition DEMO program.)

dds算法的fpga实现 altera 根据不同设置，输出不同频率的信号源-dds algorithm to achieve fpga set according to different altera, the output of the signal source at different frequencies

Digital Design and Modeling with VHDL and Synthesis

基于fpga和dsp架构的gps接收机的设计和实现(Design and Implementation of gps Receiver Based on fpga)

VHDL USB2.0接口源码,内有说明,详细.-VHDL USB2.0 interface source code, which is described in detail.

参数化FFT源代码，点数和位宽可变，内附testbench和说明文档-parameters of the source code FFT, counting and variable bit-enclosing testbench and documentation

说明：  SJA1000的ip核和相关测试脚本,OPENCORES 下载(SJA1000 IP downloads from opencores)

说明：  使用Verilog编写的24位定时器，具有apb 总线接口，可以设置工作方式和计数初值。(The 24-bit timer written by Verilog has APB bus interface, which can set working mode and count initial value.)