tcp/ip master

FPGA（现场可编程门阵列）在医疗系统中得到广泛的接受

基于FPGA的新型数据位同步时钟提取(CDR)实现方法-New FPGA-based data bit sync clock extraction (CDR) method

 音频信号先经过由运放和电阻组成的50Ohm阻抗匹配电路以满足输入阻抗50 Ohm的系统要求，这样方便信号功率的计算。为了保证所处理的信号被不失真的采样，信号还要通过截止频率为10Khz的抗混叠低通滤波器。最后为了AD能正确的采样，信号还要通过信号抬高电路。 经过12位A/D转换芯片MAX144转换后的数字信号经由基于FPGA的NIOSII处理器进行FFT变换和处理，分析各个频率点的功率值，并将这些值显示在LCD上。 该源代码就是fft变换的源代码

vhdl编程语言电子书，英文的，有很多例子(VHDL programming language e-books, in English, there are many examples of)

altera的vga示例

忆阻器的PSPICE仿真，是忆阻器的宏模型，适合于cadence16.5版本(memristor PSPICE simulation)

this project is based on sr and d flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural -this project is based on sr and d flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural

说明：  VGA图像显示，可实现图片和实现移动功能(VGA image display, enabling images and moving functions to achieve)

温度液晶显示演示程序 LCD数据线：P0口 LCD控制线：RS P20 RW P21 E P22 BUSY P07 18B20端口DQ ：P27 (Temperature of liquid crystal display demo Data line: P0 LCD LCD RS P20 RW P21 control line: E P22 BUSY P07 18B20 DQ : P27 port )

可综合的vhdl设计特点.pdf-synthesizable VHDL design features. Pdf