tcp/ip master

Xilinx FPGA block RAM reconfig via JTAG

文章运用分级抽取和多相滤波的方法改进传统CIC滤波器的结构,降低了系统工作频率,运用幅度改进函数(ACF)和外加级联余弦预滤波器的技术改进了滤波器频率响应,提出了一种高效的算法结构,改善了通带损耗,增大了阻带衰减,对CIC滤波器的实际应用和深入研究有着现实意义。 (Article the use of hierarchical multi-phase extraction and filtering methods to improve the structure of the traditional CIC filter, reducing the system operating frequency, the use of margin to improve the function (ACF) and the cosine cascade plus pre-filter technology to improve the filter frequency response, the an efficient algorithm to improve the pass-band loss, increases the stopband attenuation of the CIC filter in practical applications and in-depth study has practical significance.)

在Altera_PFGA上实现POWERLINK从站设计,这是目前最好的的最具爱的实现方案，具有很实用的参考价值。文章介绍了实现方案和主要思路。

Verilog HDL for Half Adder, Full Subtractor, Half Subtractor and 2x4 decoder.

自己在ISE下用VHDL写的UART，简单，易懂(in ISE using VHDL was the UART, simple, understandable)

有用的数字钟设计文档，有秒表、闹钟等模块，希望对大家有用！(JUST LEARN FROM IT!!ENJOY!)

说明：  该程序使用Verilog语言产生LFM信号(The program uses Verilog language to generate LFM signals.)

veirlog编写的PS2键盘通讯程序, 并有PS2接口的相关说明, Quartus II 8.1工程文件(veirlog written communication procedures PS2 keyboard, and a PS2 interface instructions, Quartus II 8.1 project file)

有关视频压缩的IPCore，希望对大家有用-Video Compression IPCore

用VHDL语言编写的LED显示器驱动电路的设计源程序-using VHDL prepared by the LED display driver circuit design source