tcp/ip master

减1计数器 一、设计要求 用Verilog HDL语言设计一个计数器。 要求计数器具有异步置位/复位功能，可以进行自增和自减计数，其计数周期为2^N（N为二进制位数）。 二、设计原理 输入/输出说明： d：异步置数数据输入； q：当前计数器数据输出； clock：时钟脉冲； count_en：计数器计数使能控制（1：计数/0：停止计数）； updown：计数器进行自加/自减运算控制（1：自加/0：自减）； load_d-a counter a reduction, design requirements using Verilog HDL design of a counter. Asynchronous requests with counter-home/reset functions can be carried out by self and self-count reduction, cycle counting of 2 ^ N (N for binary digit). Second, the principle of design input/output Description : d : asynchronous home several data input; Q : The current counter data output; Clock : clock pulse; Count_en : Counting enable control (1 : Counting/0 : Stop counting); Updown : dollars several self-Canada/reduction Operational control (1 : Since the plus/0 : Since decrease); load_d

说明：  altera ram ip教程。对RAM进行读写操作，写32个数据到RAM中，再将写入的32个数据从RAM中读出。(altera ram ip.write data to ram and read the data from the ram.)

RS编码是一种纠错码，本程序实现RS（255，223）用FPGA 实现RS编码，程序在Quartus II中调试通过。(RS coding is an error-correcting codes, the procedures for the realization of RS (255,223) with FPGA realization of RS codes, in the Quartus II program through the debugger.)

基于fpga和xinlinx ise的小游戏的vhdl程序，希望对你有所帮助！-xinlinx and they simply based on the small game and ideally the VHDL process, and I hope to help you!

I am in need of some codes of HDL

vhdl 计数器源程序，大家看看吧 vhdl 计数器源程序，大家看看吧-vhdl counter source, we see it vhdl counter source, we see it

verilog代码，串口发送接收代码，含有源代码和测试文件，准确可用(verilog code for serial port transmit and receive code, with source code and test files, and accurate available)

自己写的位同步实验程序参考，该算法需要发送和接收方的频率比较稳定时，可以很快地达到位同步，且十分稳定。位同步是通信技术的基础之一，希望对大家学习有所帮助。(The program is a reference used for bitsynchro writed by myself.When the both send s and receive s frequency are stable,the program can reach bitsynchro fastly.)

这是我从网上找到的用vhdl语言写的sdram控制器的代码。我的邮箱：wleechina@163.com-This is what I found online vhdl language used to write the sdram controller code. My mail : wleechina@163.com

Simulation and Synthesis Techniques for Asynchronous FIFO Design