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Synopsys 帮助文件 version 200205
Synopsys 帮助文件 version 200205-Synopsys sold version 200205
- 2023-08-02 16:20:05下载
- 积分:1
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离散小波变换
尊敬的先生:,
- 2022-06-19 22:22:36下载
- 积分:1
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asynchronous-fifo
同步fifo的调用程序,调用Quartus II 9.0 (32-Bit)中的fifo模块(Synchronous fifo calling program, call Quartus II 9.0 (32-Bit) in fifo module)
- 2013-08-23 21:58:56下载
- 积分:1
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Xilinx公司Accel DSP项目
xilinx accel dsp实例项目工程-xilinx accel dsp project
- 2023-03-09 20:10:02下载
- 积分:1
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M_SSB_100
由乘法器组成 单边带信号产生的 仿真源代码 msm (Composed of single sideband signal by the multiplier generated simulation source code msm)
- 2007-07-25 14:59:29下载
- 积分:1
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FSK
频移键控FSK的Verilog实现,带测试文件,并在FPGA开发板上成功验证(Frequency Shift Keying FSK the Verilog implementation, with the test file, and successfully verified in FPGA development board)
- 2020-09-03 11:28:07下载
- 积分:1
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QAM发生仿真
在Qaurtus环境下用Verilog输入实现64QAM信号的发生,用MATLAB协助验证,观察了PN序列对应的星座图。(Simulating generation of 64QAM RF Signal in Quartus II IDE,identified with MATLAB,constellation gram displayed.)
- 2021-03-02 23:39:33下载
- 积分:1
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VHDL电子钟的设计
(1)用HDL设计一个多功能数字钟,包含以下主要功能:精确计时,时间可以24小时制或12小时制显示;
(2)日历:显示年月日星期;
(3)能用QuartusII软件仿真;
- 2022-08-02 23:44:59下载
- 积分:1
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gtwizard_254_127_ex_1113_3
配置GTH ip的例子工程,选用7 series 芯片的GTH 113quad的四个通道,在程序中每个链路利用自己的恢复时钟进行数据解码,所以四个通道可以各自独立运行;成功工作在2.54Gb/s的链路状态,长时间(>24小时)的测试,误码率一直为0.(The GTH ip example project is configured with four channels of the GTH 113quad of the 7 series chip. Each link in the program uses its own recovery clock for data decoding, so the four channels can operate independently; the successful operation is at 2.54Gb/ The link state of s, long time (>24 hours) test, the bit error rate has been 0.)
- 2019-06-17 21:33:56下载
- 积分:1
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VHDLexample
VHDL开发程序,有程序仿真的截图,方便验证调试结果。并有程序说明(VHDL 驴 陋 垄 鲁 脤臑貌 拢 卢 脫臑 鲁 脤臑貌 脗脮忙渭脛 陆 脴脥 录拢卢路陆卤 茫脩茅脰 陇 渭 梅 脢脭 陆 谩 鹿 没 隆 拢 虏 垄 脫臑 鲁 脤臑貌脣渭脙 梅)
- 2008-04-10 16:11:04下载
- 积分:1