-
可以用于按键去抖动的电路应用,采用vhdl编写
可以用于按键去抖动的电路应用,采用vhdl编写-Button can be used to jitter circuit applications, the preparation of the use of VHDL
- 2022-10-29 22:25:07下载
- 积分:1
-
实现在屏幕上显示绿色和红色相间的水平条纹
实现在屏幕上显示绿色和红色相间的水平条纹。其中,vga_640x480模块将产生行同步信号hsyn和场同步信号 vsync; vga_stripes模块将产生red、green和blue三个输出。(The horizontal stripes of green and red are displayed on the screen. Among them, vga_640x480 module will produce line synchronization signal Hsyn and field synchronization signal vsync; vga_stripes module will produce red, green and blue three outputs.)
- 2020-06-24 02:00:02下载
- 积分:1
-
美国人写的各种类型的fpag设计指导,非常详细的介绍了从fpga的型号,结构,实现,编程,等各个方面的要点。...
美国人写的各种类型的fpag设计指导,非常详细的介绍了从fpga的型号,结构,实现,编程,等各个方面的要点。-Written by Americans of all types of fpag design guide, very detailed introduction from the FPGA models, structure, realize, programming, and other aspects of the main points.
- 2023-03-16 13:55:04下载
- 积分:1
-
fre
本设计是基于EP4CE15F17C8N和12864液晶的频率计程序(The design is based EP4CE15F17C8N and 12864 LCD frequency meter program)
- 2015-08-12 08:39:32下载
- 积分:1
-
3g-sdi
3g-sdi驱动器,用于全高清视频FPGA解决方案(3g-sdi driver)
- 2013-08-06 21:59:37下载
- 积分:1
-
CPU的VHDL设计代码
应用背景VHDL ;CPU设计...................................................................................................................................................................................................................................................................................................................................................................关键技术VHDL ;CPU设计...................................................................................................................................
- 2022-05-20 23:07:58下载
- 积分:1
-
RISC
32 bit RISC Processor with 3 stage pipeline
- 2010-03-03 00:09:16下载
- 积分:1
-
LCD1602测试程序
实现对LCD1602的Verilog HDL编程(the program for LCD1602 based on Verilog HDL)
- 2020-06-23 21:00:01下载
- 积分:1
-
UART
UART文件 包括发送器 接收器 fifo 测试文件(UART file includes a receiver transmitter fifo test files)
- 2016-06-06 20:35:02下载
- 积分:1
-
jtag
verilog语言编写的jtag(边界扫描模块),初学的时候可以看看(verilog language jtag (boundary scan module), a novice when you can look)
- 2021-04-27 14:38:44下载
- 积分:1