DDS Verilog 代码。包含英文文档说明

树式除法型开方器VERILOG实现,用于任意长度的无符号数的开方运算-Square root of the tree-type divider-type device to achieve VERILOG

manchester_verilog源代码(manchester_verilog source code)

xilinx FPGA 与高速ADC LVDS接口的范例程序(xilinx FPGA ADC LVDS interface)

ep2c5 实现 段寄存器 verilog语言，quartus 2 仿真-the realization of paragraph ep2c5 register verilog language, quartus 2 Simulation

一个用verilog实现的五子棋程序，用在fpga上，连接显示器，可选择与电脑对战或是双人对战，按wsad控制方向，回车控制落子，程序会自动判断输赢并显示结果(A 331 procedures implemented by verilog, used in fpga, connect the monitor, you can choose to play against the computer or a double play, press wsad control the direction, carriage control Lazi, the program will automatically determine the winners and losers and display the results)

电子闹钟：基于fpga的电子闹钟设计，采用模块化方式-Electronic alarm: FPGA-based electronic alarm clock design, modular approach

我自己当初用来求解arctan 暂时没有搞成ip形式 搞好了还要传git 这个代码还没有搞好，因为急需要下载东西 如果感兴趣可以联系我 邮件(this is a not full wrappered code very crude use chebyshev to caculate arctan function i m urgent to download a model from pudn so i do this.)

载波同步，costas环，基于Verilog的载波同步环(Carrier synchronization, costas ring, based on Verilog carrier synchronization ring )

spartan-3e vhdl fpga 输入用滑动按钮代替 输出用led代替(spartan-3e VHDL fpga input with sliding button instead of the output with led instead)

组合电路的设计8位加法器设计(ADD8.vhd)-Combinational Circuit Design 8-bit adder design (ADD8.vhd)