DDS Verilog 代码。包含英文文档说明

基于FPGA的DDS信号源设计，32位相位累加器，产生可调频率(FPGA-based DDS signal source design, 32-bit phase accumulator to generate tunable frequency)

基于FPGA的电子密码锁设计与实现，语言是VHDL语言，有注释(FPGA-based design and implementation of electronic locks, language is VHDL language, annotated)

vhdl语言，国外教材，数字信号处理算法(vhdl language, foreign materials, digital signal processing algorithms)

用verilog编写的科斯塔斯环，希望有帮助(Costas loop written in verilog helpful)

大唐电信的FPGA设计经验，内部资料，详细完整，很有参考价值-Datang Telecom

自己编的VHDL的波形发生器 做信号的可以-BOXING

基于sopc的lcd时钟，开发工具为nios ii和quartus ii9.0(Based on sopc the lcd clock, development tools for the nios ii and quartus ii9.0)

良好的Coding Style能减少Bug，减少锁存器出现的可能以及其他隐藏逻辑错误，也有助于减小芯片面积或所用资源(Good Coding Style can reduce Bug, reduce the possibility of latches and other hidden logic errors, and also help to reduce chip area or resources used.)

LED闪烁的VHDL代码

倍频器-WE