DDS Verilog 代码。包含英文文档说明

这是一个基于NIOSII的俄罗斯方块游戏设计，是基于FPGA的，利用流模式DMA传输实现游戏。(This is a box based on the Russian NIOSII game design, is based on the FPGA, and the use of streaming mode DMA transfer realize the game.)

GBT 15946-2008 GPIB可编程仪器标准数字接口的高性能协议 概述 (GBT 15946-2008 GPIB Programmable Instruments standard digital interface for high-performance protocol Overview)

code for fft non synthesisable in xilinx ise

高级FPGA设计__结构、实现和优化,中文翻译版(Advanced FPGA Design- Architecture, Implementation, and Optimization)

基于VHDL语言的串口发送和接收程序,自己调试通过，并已经运用在工程中(Based on the serial port to send and receive procedures VHDL language, its own debugging, and has been used in the project)

4位的超前进位加法器，门级电路连接得到，verilog代码实现(4-bit look-ahead adder, gate-level circuit)

使用Verilog语言对128点 基8FFT的实现(Implementation of 128-point basis 8FFT)

用Verilog HDL编写的VGA显示驱动程序-Verilog HDL prepared with VGA display driver

Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.

simple code based on verilog shifter , cla ,clg