DDS Verilog 代码。包含英文文档说明

FPGA的仿真实例，Verilog代码编写，过程详尽，代码易懂。-FPGA simulation examples, Verilog coding, the process in detail, code easy to understand.

本实例用于SDRAM完成读写功能: 先向SDRAM里面写数据，然后再将数据读出来做比较，如果不匹配就通过LED变亮显示出来，如果一致，LED就不亮。(The examples for SDRAM read and write functions.)

6713emiftofpgatopci,这个是完整的一套从6713的emif到fpga的双口ram，然后主机通过9054到双口ram，交换数据完成-6713emiftofpgatopci, this is a complete set of the EMIF from 6713 to the FPGA

硬件描述语言Verilog-Verilog hardware description language

VGA彩条信号显示控制电路设计,能通过vga显示横条纹竖条纹棋盘条纹(VGA color signal display control circuit design)

SMT32F4 i2s 全双工配置，自己测试OK的，大家可以看看(SMT32F4 i2s 全双工配置)

SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals in various formats. The cores connect using AXI-streams. Most configurations (resolution, framerate, colordepth, etc.) are set at compile-time using Verilog parameters. See svo_defines.vh for details on those parameters.

小波变换的VHDL代码，内带正变换逆变换的测试文件。(Wavelet transform VHDL code, with a positive transformation within the inverse transform of the test file.)

JPEG标准下图象压缩的vhdl实现工程，文件包括一个图像。-JPEG image compression standard works of VHDL realize that the document includes an image.

实现简单自动售货机的基本功能。投币找零功能，并用Led数码管显示，输出结果用Led显示。(Basic functions simple vending machines. Coin change for function and use Led digital tube display, the output display Led.)