DDS Verilog 代码。包含英文文档说明

说明：  fpga版本的数码管动态扫描程序，可供学习(FPGA version of the digital tube dynamic scanning program for learning)

VHDL语言教材-The teaching material of VHDL Language

SDRAM 控制器的多 CPU 系统的公断人将调度内存访问。

calculate min max of series of nb

FIFo参考设计16x32 FIFO with simultaneous read/write operations.-FIFO design-16x32 FIFO with simultaneous read/write operations.

fault minimization using genetic algorithm

一种十字路口交通灯在matlab环境中的实现源码(Traffic lights at the crossroads)

VC++6.0软件生成Altera公司FPGA内部存储器ROM初始化数据mif格式文件。方便通过QuartusII导入波形等参数。强调这个是例子，生成的是一个定点的正弦数据表文件，需要用到的请自行修改源代码。(This software generates internal memory ROM initialization mif format data file for FPGA product by Altera. Facilitate the passage of the waveform parameters such as import QuartusII)

super fast debounce button on vhdl, xilinx xc

FPGA控制的SRAM接口不分的设计-FPGA-controlled SRAM interface design, regardless of