用VHDL语言实现的ARM处理器的标准内核的源代码程序，可在重用...

vhdl写的ds18b20程序，相互交流-vhdl written ds18b20 procedures, mutual exchange

Use this multimeter to make precise electronic measurements and tests. Easy-to-read LCD readout, positive set selector switch and 32" leads. AC voltage

 音频信号先经过由运放和电阻组成的50Ohm阻抗匹配电路以满足输入阻抗50 Ohm的系统要求，这样方便信号功率的计算。为了保证所处理的信号被不失真的采样，信号还要通过截止频率为10Khz的抗混叠低通滤波器。最后为了AD能正确的采样，信号还要通过信号抬高电路。 经过12位A/D转换芯片MAX144转换后的数字信号经由基于FPGA的NIOSII处理器进行FFT变换和处理，分析各个频率点的功率值，并将这些值显示在LCD上。 该源代码就是fft变换的源代码

说明：  经过验证的经典实例，完全正确的。适合于入门新手的实例，仅供交流使用。(fpga exampe)

可以实现对任意波形分任意频，分频加减通过按键实现。-Can be achieved for any arbitrary waveform at frequency, frequency addition and subtraction through the keys to achieve.

合并单元内GPS同步时钟的检测 合并单元内GPS同步时钟的检测-Combined unit GPS clock synchronization detection unit merger GPS synchronized clock detection

dsp与fpga通信的verilog程序，强烈推荐欢迎参考(dsp and fpga verilog communication program, it is strongly recommended to welcome reference)

LPC总线从设备的verilog设计,包含状态机和中断功能。-verilog code for LPC device

用FPGA实现DDS,可变频,幅值由硬件完成-Using FPGA realize DDS, can be frequency, amplitude from hardware to complete

基于ALINX AX7020硬件平台的USB-OTG通信程序。操作系统采用uCOS III v1.41，基本实现了双向USB2.0 块传输（Bulk Transfer）通信，zynq的PS端接收USB数据并回传至主机。经测试，主机端Window10系统采用libUSBK编程时，采用64字节的块时，传输速率可达210Mbps。zynq开发工具为Vivado2015.4，程序包中包含了全部的硬件和软件工程文档。(A USB-OTG communication project where an AX7020 platform is employed as USB device. The embeded operating system is uCOS III of version 1.41, and the FPGA toolchain is Vivado 2015.4. This project implements a full speed bidirectional USB2.0 bulk transfer. A test on Windows 10 host with libUSBK shows that the transfer speed is up to 201Mbps.)