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VHDL digital system design and engineering practice 4, including the principles,...
VHDL数字系统设计和工程实践5,包含原理,真值表和原理图,以及VHDL源代码.-VHDL digital system design and engineering practice 4, including the principles, truth table and schematic, as well as VHDL source code.
- 2022-08-11 13:48:51下载
- 积分:1
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adder
This the adder VHDL code, it contains input and output fild, also simulate file-adder
- 2022-06-21 18:48:32下载
- 积分:1
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QPSK_System
实现QPSK系统的调制解调仿真,基带成形滤波器采用升余弦滚降滤波器,将仿真的误码率与理论误码率作了比较(Implement QPSK modulation and demodulation simulation system, the baseband shaping filter using Raised Cosine filter will BER simulation were compared with the theoretical BER)
- 2020-12-22 15:39:07下载
- 积分:1
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seg7
SEG7数码管显示示例程序,适用于ALTERA的CPLD(SEG7 digital display sample program of ALTERA CPLD)
- 2012-05-31 10:29:25下载
- 积分:1
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IEEE Standard for Verilog 2005
IEEE Standard for Verilog 2005
- 2017-06-05 13:53:12下载
- 积分:1
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LZRW1 VHDL语言,有有下
lzrw1算法,VHDL语言,不带TB。模块验证,自己写TB文件
- 2023-05-21 19:15:03下载
- 积分:1
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XUAN-ZHUAN-led
旋转LED 实现自适应转速 字幕滚动 对接的程序(Rotating LED Adaptive Speed subtitles scroll docking program)
- 2013-02-06 16:17:56下载
- 积分:1
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基于FPGA的交通控制器
设计一个由一条主干道和一条支干道的汇合点形成的十字交叉路口的交通灯控制器: 1) 主、支干道各设有3个方向的绿、黄、红指示灯(左转、直行和右转),每个行驶方向均配有时间显示数码管;2) 主干道处于常允许通行状态,而支干道有车来才允许通行(由外部信号通知)。3) 当主、支道均有车时,两者交替允许通行,主干道每次放行90s,支干道每次放行60s,在每次由亮绿灯变成亮红灯的转换过程中,要亮5s黄灯作为过渡,并进行减计时显示。
- 2022-02-26 08:00:04下载
- 积分:1
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FFT
FFT with FIR created by students in univercity
- 2015-06-22 14:57:30下载
- 积分:1
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AMBA
AMBA总线规范,能对从事嵌入式的同行们有一些帮助,让大家更好的理解ARM 结构和AMBA 体系(AMBA Specification)
- 2012-12-06 20:35:22下载
- 积分:1