高速FIFO，verilog设计。速度高达130Mhz

IIC slave controller source code

利用FPGA实现硬件的VHLD语言的Manchester code。(Hardware implementation using FPGA VHLD language Manchester code.)

early branch rename table(store rename table once the branch instruction comes in. Used in out of order pipeline processor)

FFT程序，此程序虽然耗逻辑资源很大，但是在接受数据后的第7个时钟沿就可以输出FFT变换后的数据，对要求时延较低的系统可以考虑-FFT procedure, this procedure should not consume a lot of logic resources, but the data in the first seven clock can be output along the FFT transformed data, the requirements of time-delay system can be considered lower

很多实用的例程，包括触发器，译码器，多路选择器-A lot of useful routines, including the flip-flop, decoder, MUX

表决器，简单实现了表决功能，无显示功能 -vote

采用Verilog HDL语言编写的直流电动机控制系统，主要完成直流电动机的速度控制，典型的三闭环(位置、转速和电流反馈)直流电机控制系统，对控制类相关的学习者价值很高(Using Verilog HDL language of the DC motor control system, mainly the completion of DC motor speed control, a typical three-loop (position, speed and current feedback) DC motor control system for control-type high-value related to the learner)

说明：  ADV7179芯片的驱动程序，基于FPGA硬件实现，已经验证可以使用(ADV7179 chip drivers, FPGA-based hardware implementation has been verified using)

利用cordic实现直角坐标与极坐标的转换，用vhdl实现-use cordic achieve very Cartesian coordinates with the conversion, with vhdl achieve

ES A PRACRICA 2 DEL LABORATORIO DE DIGITAL