高速FIFO，verilog设计。速度高达130Mhz

实现基于FPGA的控制MCP2515发送的程序，本人编写通过测试，希望提供帮助(FPGA-based control program sent MCP2515, I write to pass the test, hoping to help)

THE SOURCE REALIZE THE TRANSFORMATION FROM YUV TO RGB

一个vhdl实现的测频计,开发环境为任何支持vhdl语言的厂商提供的开发环境 -VHDL achieve a frequency measurement of dollars, development environment for any VHDL language support for manufacturers of the development environment

verilog hdl教程135例:verilog hdl语言类似于C语言，便于学习。本文档带有源代码，3-6章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code, 3-6

8位相 加乘法器，具有高速，占用资源较少的优点-eight multiplier phase together with high-speed, taking up less resources advantages

采用costas环进行DPSK解调的程序。输入数据速率2.4Kbps，载波频率12KHz，采样率1.6MHz， 输入数据位宽12位，快捕带为799.617Hz(Costas ring using DPSK demodulation process. Input data rate 2.4Kbps, carrier frequency 12KHz, sampling rate 1.6MHz, the input data 12 bits wide, fast catching band is 799.617Hz)

基于ATEREAL EPM1270T144C5N CPLD 压力传感器数据采集原码 开发软件 Quartus II -ATEREAL EPM1270T144C5N CPLD-based pressure sensor data acquisition source Quartus II development software

用VHDL写的4*4乘法器，学习VHDL语言的可以-Use VHDL to write the 4* 4 multiplier, learning VHDL language can be

数码扫描显示转换模块，可以对数码内容进行扫描，同时可进行转换-digital scan conversion modules, the digital content can scan, which can also be converted

关于vhdl的一些例子-on some of the examples of VHDL