高速FIFO，verilog设计。速度高达130Mhz

支持GF(2^n)域的rs编解码，可直接修改参数实现不同方式的RS编码和解码(This program is an encoder/decoder for Reed-Solomon codes.)

UART communication on SPARTAN 6 it contains tx and rx

密码锁 vhdl实现的密码锁 控制程序-mimasuo

机器人控制,用matlab robotics toolbox 仿真设计(robotics controll using matlab robotics toolbo simulation)

说明：  基于Xilinx Spartan6系列的fpga的VGA实现(Based on Xilinx Spartan6 series fpga VGA implementation)

使用CycloneIV芯片，实现对高精度ADCad9226的数据采集。内有详细代码说明，并附有调试结果(Use CycloneIV, to achieve high-precision data acquisition ADCad9226. Along with debugging results)

采用FPGA实现打车计程系统设计，实现自动计程及计费，本内容包括硬件程序设计及基于QUARTUS软件的仿真

企业用verilog代码风格规范 本规范规定了IC设计项目开发过程中VerilogHDL源代码的编写总则、要求及模板文件。(Enterprises with verilog code style guide for the preparation of this specification General IC design project development process VerilogHDL source code, requirements and template files.)

In this case is a QPSK algorithm code for mapping the interleaved code, using VHDL language. This code provide the method of mapping the code by using QPSK algorithm.

encoding and decoding of audio signal