高速FIFO，verilog设计。速度高达130Mhz

高速串行设计FPGA-GTX IP设置生成drp模块，可动态配置速率2.4Gbps，1.2Gbps，0.6Gbps，自适应链接(High-speed serial design FPGA-GTX IP setting generation drp module, dynamically configurable rate 2.4Gbps, 1.2Gbps, 0.6Gbps, adaptive link)

VHDL语言编写的FIR滤波器源码 对于嵌入式设计者有很好的指导作用 -VHDL prepared by the FIR filter source for Embedded designers have a good role in guiding

VHDL拔河电路的设计 基于cyclone V  VHDL拔河电路的设计 基于cyclone V VHDL巴赫电路的设计 基于cyclone V VHDL巴赫电路的设计 基于cyclone V VHDL巴赫电路的设计 基于cyclone V

SDRAM控制器源码，内含完整的控制器verilog源代码和测试代码，超值哈。(This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1.)

vhdl,双向移位寄存器，实现置数，左移及右移操作-vhdl, bi-directional shift register to achieve set the number of left and right shift operation

verilog HDL经典的入门书籍，内容很详细，讲了许多实例，适合硬件描述语言初学者。(verilog HDL classic introductory book, the content is very detailed, spoke many instances, suitable hardware description language for beginners.)

本例为TLC7524接口电路VHDL原程序-Example for the TLC7524 interface circuit VHDL original procedure

低密度校验码 ，很好用的代码，功能已经实现编码和译码(fpga ldpc)

USB 1.1 PHY的代码，verilog语言 USB 1.1 PHY的代码，verilog语言-USB 1.1 PHY code, verilog language USB 1.1 PHY code, verilog language

通过PC串口调试助手向MINI板发数据（HEX），在数码管显示接收到的数据，并回传给PC(The debugging assistant sends data (HEX) to MINI board through PC serial port, displays the received data in the digital tube and sends it back to PC)