altera DE1 SD_CARD带写入一个扇区功能的程序，已确认成功，下载直接运行就可以看效果...

verilog编写的数字信号发生器NCO用CORDIC方法实现产生sin cos信号，流水线结构，简单实用。(verilog prepared by the digital signal generator NCO using CORDIC method implementation generate sin cos signal, pipelined architecture, simple and practical。)

crc5 bolck in usb contreoller

说明：  ethernet mac vhdl verilog basic

ＦＰＧＡ在通信上的运用：基于VHDL的帧同步程序(Application of FPGA in communication: Based on VHDL frame synchronization procedures )

说明：  功能是（用Verilog语言的，内有比较详细的注释）： （1）计数器的功能是从0到9999计数，并能以十进制数的形式在七段数码管上显示出来(包括七段数码管显示模块). （2）该计数器有一个1个nclr和一个adj_plus端，在控制信号的作用下（见下表），计数器具有复位、增或减计数、暂停的功能。编写以上的程序的完整模块. 计数器的功能表 nclr adj_minus 功 能 0 0 复位为0 0 1 递增计数 1 0 递减计数 1 1 暂停计数 (Function is (with Verilog language, the more detailed comments): (1) counter function is from 0 to 9999 counts, and are able to form a decimal number on the seven-segment LED display (including the seven-segment LED display module). (2) The counter has a one nclr and a adj_plus side, under the action of the control signal (see below), the counter has reset, increase or decrease of count pause function. Complete the preparation of the above program modules. Counter function menu nclr adj_minus reset 0 0 0 0 1 1 0 counts counting suspended Count 1 1)

可综合的vhdl设计特点.pdf-synthesizable VHDL design features. Pdf

PS2 Module for Altera DE2

说明：  APPCM算法和AD/DA芯片驱动在CPLD中的实现，已在实际硬件中测试OK，quartus2环境(APPCM algorithm and AD/DA chip in the drive to achieve in the CPLD has been tested in actual hardware OK, quartus2 environment)

是用于pci开发的核，可以将硬件的信息映射到然间上来 节省出开发人员用于了解硬件的时间 (Pci developed for nuclear, hardware information can be mapped to the inter-ran up to save the developers time to understand the hardware)

这是很全的标准库啊，不是1164.vhd，都是一些加，乘，除，平方等操作的包来的．-This is the standard for the whole ah, not 1164.vhd are some increases, multiplication, addition, operational square packages to come.