sm4 vhdl

DDR2 SDRAM 控制器的FPGA实现-DDR2 SDRAM controller FPGA to achieve

VHDL_COUNTING 000_255 液晶显示器 (ĐẾM 000 ĐẾN 255 HIỂN THỊ 液晶电视 BẰNG NGÔN NGỮ VHDL)

在利用Verilog在FPGA平台上输出正弦波，实现芯片为Cyclone II 484C8，有管脚分配-In the use of Verilog in the FPGA platform, the output sine wave, the realization of the chip for Cyclone II 484C8, has pin allocation

说明：  SJA1000的ip核和相关测试脚本,OPENCORES 下载(SJA1000 IP downloads from opencores)

数字秒表的实现，我还写个具体的过程要求等，(there is function of clock,it very useful)

基于FPGA的交通灯代码，VHDL语言书写。适合新手学习vhdl语言时使用(FPGA-based traffic light code, VHDL language writing. Suitable for novice learning vhdl language used when)

说明：  All AMBA bus protocols - AXI3, AXI4, AXI4-Lite, ACE, AHB

项目目的是设计 DCT 和 IDCT 在 VHDL 中。离散余弦变换图像压缩中用于压缩的 JPEG 图像。此文件包含 DCT 和 IDCT 块和顶级模块于一体的两个块和矢量来测试这两个模块。

能够在EDA环境下实现四位十进制数字密码锁的设置与开锁功能，并能更改使用密码，还可以防止抖动(EDA environment to achieve four decimal code lock and unlock function of the settings and change the use of passwords, but also to prevent the jitter)

I2C总线芯片AT24C02程序设计 C++编程(I2C bus AT24C02 chip program design)