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RS_Encode_Decode
RS(255,223)编解码算法。verilogHDL代码实现,在XILINX的芯片上得到验证。不包含任何IP核,方便移植到任何FPGA芯片。(RS (255223) encoding and decoding algorithm. VerilogHDL code to achieve, in the XILINX chip to be verified. Does not contain any IP core, easy to transplant to any FPGA chip.)
- 2016-01-21 12:07:34下载
- 积分:1
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VHDL参考程序,他们的初学者参考使用
vhdl参考程序,供初学者参考使用-VHDL reference procedures, their use and reference for beginners
- 2022-04-19 08:23:59下载
- 积分:1
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DE2 development company for the altera board SD_Card_Audio examples
用于altera公司DE2开发板上SD_Card_Audio的实例-DE2 development company for the altera board SD_Card_Audio examples
- 2022-12-25 12:55:03下载
- 积分:1
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I2C
VHDL语言编写的I2C通信接口,可与单片机等MCU相连,只占用很少的引脚线完成数据的传输(Written in VHDL I2C communication interface, such as MCU and MCU can be connected, only takes a few lines to complete the data transmission pin)
- 2011-05-15 09:00:33下载
- 积分:1
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Key_gen the Qutuas II v7.1 for sp1 invalid This is the v7.1 sp1 months key_gen
Qutuas II v7.1的key_gen 对sp1无效
这就是个v7.1 sp1的key_gen
-Key_gen the Qutuas II v7.1 for sp1 invalid This is the v7.1 sp1 months key_gen
- 2023-07-28 18:25:02下载
- 积分:1
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SourceFile
PS2键盘实验Verilog HDL代码(PS2 keyboard experiment Verilog HDL code)
- 2008-03-15 01:14:55下载
- 积分:1
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vhdl
说明: vhdl常见小实验代码,包括二进制比较器,4选1,8421十进制,8421转化成格雷码,8421余三码,分频器,数据码译码器,二进制减计数器,四位环形计数器等(VHDL common small experiment code)
- 2020-06-24 13:00:02下载
- 积分:1
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半加器
半加器
- 2022-10-16 16:40:03下载
- 积分:1
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编译实现循环码的产生,用FOR循环分别对其中的码元进行设置。...
编译实现循环码的产生,用FOR循环分别对其中的码元进行设置。-Implementation cycle of the compiler generated code, respectively, using FOR Cycle one of the key element of the set.
- 2022-08-11 07:55:45下载
- 积分:1
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AlteraFPGA_CPLD
ALTERA FPGA CLPD
- 2010-04-11 14:52:36下载
- 积分:1