介绍了硬件语言的仿真软件modelsimse的操作是使用方法，可以为入门的参考资料...

用VHDL语言设计多功能的电子表。实现基本电子表的时间显示、闹钟、秒表等功能(VHDL language design with multi-functional electronic watch. The time table to achieve basic electronic display, alarm clock, stopwatch functions)

AXI4-Lite总线的主从机读写，例程及代码(AXI4-Lite Bus Host-Slave Read-Write, Routine and Code)

用VHDL实现频率计，可测量输入脉冲的频率，并进行简单校正(Realize the frequency of use of VHDL in terms of measurable input pulse frequency, and a simple correction)

上海交通大学电子信息与电气工程学院VHDL经典教程-Shanghai Jiaotong University Electronic Information and Electrical Engineering, Institute of Classical VHDL Tutorial

《Altera FPGA_CPLD设计 高级篇》详细介绍FPGA应用于高级特性，LogicLock设计，时序约束，设计优化，高级工具及系统级设计技术，是深入学习FPGA的重要材料(" Altera FPGA_CPLD advanced part design" details FPGA used in advanced features, LogicLock design, timing constraints, design optimization, system-level design tools and advanced technology, in-depth study is an important material for FPGA)

Free 8051 core upload

说明：  XC7A35TCSG324-1的Verilog频率计程序，支持十分频，支持切换内外信号输入(Verilog frequency meter program of xc7a35tcsg324-1 supports decadal frequency division and switching internal and external signal input)

verilog支持noise噪声的端口port, 可以用于仿真运行. 评估噪声影响 Verilog port that supports noise and can be used for simulation run. Evaluate noise effects

对PCM编码的多路复用与解复用程序，VerilogHDL源程序-Of PCM-encoded multiplexing and demultiplexing process, VerilogHDL source

Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate model * Synthesizable VHDL model -Turbo Decoder Release 0.3* Double binary, DVB-RCS code* Soft Output Viterbi Algorithm* M yHDL cycle/bit accurate model* Synthesizable VHDL model