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16QAM
16QAM调制解调程序画出时域波形、 正交分量、同相分量波形,眼图,散点图等(16QAM modulation and demodulation process to draw time-domain waveform, quadrature components, in-phase component waveforms, eye diagrams, scatter plots, etc.)
- 2013-06-04 22:10:41下载
- 积分:1
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SDC_RDC
基于FPGA的双通道旋转变压器测角系统硬件设计,分析的比较清楚。(FPGA based dual channel rotary transformer angle measurement system hardware design, analysis of the relatively clear.)
- 2011-08-07 20:23:10下载
- 积分:1
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M_M
此为数学形态滤波器消燥的代码,用于一维信号,涉及一个具体的例子,需要的话可以自己修改,修改相应的结构元素。(This is a mathematical morphology filter away dry code, used to one dimensional signal, involving a concrete example, necessary can change ourselves, change the structure of the corresponding elements)
- 2013-08-29 21:36:37下载
- 积分:1
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Keil C51和A51,AVR uedit x86汇编的亮点,VHDL格式
Uedit中对Keil C51、A51、avr、x86汇编以及VHDL语言的突出显示格式文件-Uedit of Keil C51, A51, avr, x86 VHDL compilation of the highlights format
- 2023-05-12 11:00:04下载
- 积分:1
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数控分频器设计:对于一个加法计数器,装载不同的计数初始值时,会有不同频率的溢出输出信号。计数器溢出时,输出‘1’电平,同时溢出时的‘1’电平反馈给计数器的输入端...
数控分频器设计:对于一个加法计数器,装载不同的计数初始值时,会有不同频率的溢出输出信号。计数器溢出时,输出‘1’电平,同时溢出时的‘1’电平反馈给计数器的输入端作为装载信号;否则输出‘0’电平。
-NC divider design : an adder counter, loading the initial count value, have different frequency output signal of the overflow. Counter overflow, the output"1 "Level, Overflow at the same time the"1 "level feedback to the counter input signal as loading; Otherwise output"0 "level.
- 2022-04-28 17:05:55下载
- 积分:1
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VHDL38decoder
VHDL 语言实现 38译码器 文件中包括 程序 源代码 还有 testbench 测试程序(38 decoder VHDL language implementation, including program source code file, there are testbench test procedures)
- 2020-06-29 23:40:03下载
- 积分:1
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Verilog-
VHDL的基本语法,应用,建模,编程示例等...(Introduction to VHDL basic syntax, applications, modeling, programming example and so on ...)
- 2012-03-13 19:59:29下载
- 积分:1
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MAX262
MAX262是一款可程控滤波芯片,该是它的英文数据手册.(MAX262 is a programmable filter chip, which is its data sheet in English.)
- 2007-08-14 16:32:01下载
- 积分:1
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pex8311代码实现
pex8311代码实现 altera的fpga 代码编程 实现本地读写 pex8311_test
- 2022-01-28 06:56:26下载
- 积分:1
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uart(可综合)
说明: 【实例简介】用Verilog实现uart串口协议,波特率可选9600、19200、38400、115200。8位数据为,1位校验位,1位停止位。
【实例截图】
【核心代码】核心代码包括TX,RX,Baud,FIFO([example introduction] UART serial port protocol is implemented with Verilog, and the baud rate can be 9600, 19200, 38400, 115200. 8-bit data, 1 bit check bit, 1 stop bit.
[example screenshot]
[core code] the core code includes TX, Rx, baud and FIFO)
- 2020-12-08 16:00:16下载
- 积分:1