USB接口控制器参考设计VHDL代码,方便开发FPGA人员进行USB的开发，是一个不错的源码。...

译码器，将八位输出转换为七段译码显示，相当于7448驱动译码管-Decoder, the 8 output is converted to seven segment decoding shows that the equivalent of 7448

华为文档《硬件描述语言Verilog基础》-目录 原来搞VHDL，刚刚开始学Verilog。觉得这个入门的提纲不错，共享一下。 (Huawei Documents " basic Verilog Hardware Description Language" - the original directory engage in VHDL, just beginning to learn Verilog. Feel that the entry of the outline of a good, share some.)

正弦波UPS中的逆变电路 包括原理分析 框图 及原理图(Sine wave UPS inverter circuit the principle analysis block diagram and schematic)

NN CONTROLLER FOR UPQC

图像处理的中值滤波器，使用verilog开发环境编程实现。(Verilog development environment programming median filter)

RS码的FPGA编码文件，QUARTUS工程(The RS codes FPGA encoded file, QUARTUS engineering)

altera公司飓风四代芯片，LCD屏幕彩条显示，有效实现行、场扫描。练习FPGA驱动VGA或LCD显示的入门程序(Altera hurricane four generation chip, LCD screen color display, the effective realization of line and field scanning.Practice FPGA to drive VGA or LCD display)

FFT with FIR created by students in univercity

说明：  2018全国大学生FPGA创新设计大赛南京总决赛封闭测试题目，以及自己编写的verilog和testbench，欢迎学习借鉴(The closed test topic of the 2018 National Undergraduate FPGA innovation design competition Nanjing finals, as well as Verilog and testbench compiled by ourselves, are welcome to learn)

EDA用maxplus2开发设计的简易数字钟，适合初学者，vhdL语言(EDA maxplus2 in development and design of simple digital clock, is suitable for beginners, vhdL language )