中值滤波

Efficient CIC filter Implementation using VHDL

This a verilog file which is used as a decoder-This is a verilog file which is used as a decoder

完整的GMSK调制及维特比译码，程序中包括了高斯滤波器的设计，调制相位的计算，并采用了维特比译码算法解调出原始码元，最后计算了其误码率。(Complete GMSK modulation and Viterbi decoding, the program includes a Gaussian filter design, the calculation of the phase modulation, and uses the Viterbi algorithm demodulates the source element, the final calculation of the bit error rate.)

DDS中的正余弦生成，初始相位相差90度，可自行改变输出频率(Cosine generation of DDS, the initial phase difference of 90 degrees, the output frequency can be changed on their own)

用Verilog HDL语言编写的AT24C04程序，并用数码管显示，已经过测试，很好用-With the Verilog HDL language of the AT24C04 procedures and use digital tube display, has been tested, very good to use--

基于DDS的信号发生器设计。DDS,FPGA,Verilog。(Design of signal generator based on DDS.DDS,FPGA,Verilog.)

说明：  使用Verilog，以Quartus II 为平台，编写了一个DDS信号发生器程序。(Using Verilog and Quartus II as the platform, realizing the DDS signal generator program .)

ac97 VHDL core

controller for sending serial data at different speeds

数字时中（VHDL）-Numbers in (VHDL)! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !