中值滤波

关于5-11APSK在高斯信道中的误码率分析仿真程序，对具体调制方式及解码方式都有详细的过程(About 5-11APSK in Gaussian channel bit error rate analysis simulation program, has a detailed specific modulation and decoding process)

Used for Time shifting discrete signals, it can do both integral and fractional sampling period delay. Original.

（1）用HDL设计一个多功能数字钟，包含以下主要功能：精确计时，时间可以24小时制或12小时制显示； （2）日历：显示年月日星期； （3）能用QuartusII软件仿真；

v6 1x 3.125G rapidio协议工程代码(xilinx v6 rapidio data transmission protocol Practical project application engineering code)

有用的数字钟设计文档，有秒表、闹钟等模块，希望对大家有用！(JUST LEARN FROM IT!!ENJOY!)

说明：  BT656 时序, 逐行, 分辨率1280*960@25Hz(BT656 time series, row by row, resolution 1280*960@25Hz)

这是一本关于verilog编程语言的教程,对学习verilog语言有帮助-This is the one on the Verilog programming language tutorial, Verilog language learning has helped

完整版的乘法器.相信对初学者有不小的提高-The full version of the multiplier. I believe there is not a small improvement for beginners

若农场路无车辆，则在高速路保持绿灯。在探测农场路有车辆，高速路上的交通灯应由绿到黄，再到红，并允许农场路方向灯变绿，绿灯亮一段时间，由绿变黄再到红。(If there is no vehicle on the farm road, keep the green light on the highway. There are vehicles on the farm road, the traffic lights on the high speed road should be green to yellow, and then red, and allow the farm road lights to turn green, the green light for a period of time, from green to yellow, then to red.)

FPGA based implementation of a SDR - codes in Verilog HDL for the processor and control.-FPGA based implementation of a SDR- codes in Verilog HDL for the processor and control.