FIR filter basic verilog code for implementation

FFT变换的IP核的源代码 VHDL~-FFT IP core of the source code for VHDL ~

ＡＤ转换代码，主要练习，没有具体的功能可以实现的，因为只是一部分(AD conversion code, practice, no specific function can be realized, because only part)

基于quartus 的一些程序 都是verilog 还是比较有用的 -Based on some of the procedures Quartus Verilog are still quite useful

由忆阻器机制设计蕴含逻辑，内含testbench仿真文件(Design implied logic by memristor mechanism, including testbench simulation file)

代码实现了一个由32位寄存器组成的寄存器组，并有多个控制输入和两个输出，方便使用。(The code implements a 32-bit register consisting of registers, and there are multiple control inputs and two outputs, easy to use.)

FPGA SPI 主要模块全部涵盖 时序解释 与DSP通信(FPGA SPI Timing interpretation covering all main modules communicate with the DSP)

VHDL实例这是我下载到的最好的VHDL实例，看完这些实例，可以使你有一个长足的进展-VHDL example

4X4keypad的防抖动模块，用于假按键的检测-4X4keypad shake the module, the keys for false detection

一位全加器的VHDL源码与TEST BENCH.XILINX下通过(A full adder and the VHDL source code through TEST BENCH.XILINX)

本实验实现了一个小的乒乓游戏，VGA显示,代码下载的FPGA板子上验证通过，效果很好。(The experimental realization of a small ping-pong game, VGA display, download the code verified by the FPGA board, with good results.)