The use of FPGA to collect the new U.S. accelerometer data and the data collecte...

说明：  30 bus for atp design

说明：  基于Xilinx Spartan6系列的fpga的VGA实现(Based on Xilinx Spartan6 series fpga VGA implementation)

d5m的DE2驱动Verilog HDL (d5m driven on DE2 by Verilog HDL )

关于USB开发的verilog开发程序，非常的全面，学习FPGA开发时用得着。(About USB development verilog development process, very comprehensive, learning FPGA development time worthwhile.)

说明：  使用VHDL语言写的AVR单片机IP核， 可以直接使用，已经经过验证， 十分珍贵哦(Written in VHDL language using the AVR microcontroller IP core, can be used directly, has proven very valuable oh)

基于FPGA的乐曲发生器电路设计 附含源代码（quartersii环境下运行）-FPGA-based circuit design of the music generator containing the source code is attached (quartersii environment to run)

基于nios ii 控制altera de1 开发板上iic总线实现与at24c02通信-Based on nios ii controlled altera de1 Development Board iic bus for communication with the at24c02

软件环境：TI的zstack协议栈 硬件：CC2530无线单片机 功能：利用超声波模块实现测距（该模块型号：HC-SR04 在淘宝上非常常见） 可测2厘米到3米距离(Software environment: TI' s zstack protocol stack hardware: CC2530 wireless microcontroller features: use of ultrasonic ranging module (the module Model: HC-SR04 on Taobao very common) can be measured 2 cm to 3 meters)

说明：  FIFO: First in, First out 代表先进的数据先出，后进的数据后出。Xilinx 在 VIVADO 里为我们已经提供了 FIFO 的 IP 核, 我们只需通过 IP 核例化一个 FIFO，根据 FIFO 的读写时序来写入和读取FIFO 中存储的数据。(FIFO: first in, first out represents the first out of advanced data, and the last in data is the last out. Xilinx has provided us with the IP core of FIFO in vivado. We only need to instantiate a FIFO through the IP core, and write and read the data stored in FIFO according to the FIFO read-write timing.)

这个是vhdl中很常见的jk filpflop的文件只用于很小数位的变化 其中的jk文件是up down运算都符合的(This is a very common vhdl jk filpflop file is only used for very small changes in a digital file which jk is up down operations are met)