运行在FPGA上的Verilog程序(实现对ADC的控制)

基于labview的数据采集系统，包括示波器和函数信号发生器，可以实现简单数据采集.(Labview-based data acquisition system, including oscilloscopes and function signal generator, can achieve a simple data acquisition.)

c54x的VeriLog程序代码 也是opencoreip-C54x is the Verilog code opencoreip

描述了使用FPGA接口PDIUSBD12开发USB接口的流程.-Describes the use of FPGA Interface USB interface PDIUSBD12 development flow.

DA9125 配置spi程序 正弦波产生(DA9125 configuration spi program sine wave generated)

adpcm .c程序代码，完整,通过编译仿真(ADPCM c program code, complete compiled simulation)

have a good documenty

文件中包含BFSK、DPSK、BPSK、QPSK等等数字调制程序。(File contains the BFSK, DPSK, BPSK, QPSK, and so on digital modulation process.)

  基于FPGA(Field-Programmable Gate Array)的OFDM(Orthogonal Frequency Division Multiplexing)信号传输系统VHDL源码 use IEEE.std_logic_unsigned.all; package outconverter is constant stage : natural := 3; constant FFTDELAY:integer:=13+2*STAGE; constant FACTORDELAY:integer:=6; constant OUTDELAY:integer:=9; function counter2addr( counter : std_logic_vector; mask1:std_logic_vector; mask2:std_logic_vector ) return std_logic_vector; function outcounter2addr(counter : std_logic_vector) return std_logic_vector; end outconverter; package body outconverter is function counter2addr( counter : std_logic_vector; mask1:std_logic_vector; mask2:std_logic_vector ) return std_logic_vector is variable result :std_logic_vector(counter"range); begin for n in mask1"range loop if mask1(n)="1" then result( 2*n+1 downto 2*n ):=counter( 1 downto 0 ); elsif mask2(n)="1" and n/=STAGE-1

74ls165电路源代码verilog,已经验证。(74ls165 verilog)

Syllabus for VSC-HVDC course