vhdl 加法器 vhdl 加法器 vhdl 加法器

verilog语言实现一个CPU，汇编程序实现汉明编码功能，输入11位代码，输出15位编码结果。(Verilog language to achieve a CPU, assembler to achieve Hamming coding function, enter 11 bit code, output 15 bit encoding results.)

说明：  在MATLAB下自编实现快速傅里叶分析，(Fast fft own procedures, faster than the system call fft slowe)

VHDL Programmes -2 for dumping on FPGA

AES 128 bit with various device interface on FPGA

有关于SD卡的音频部分！希望对大家有用！-SD cards have on the audio portion! Hope useful for everyone!

一个8位CISC结构的精简CPU，2还提供了编译器-an eight streamline the structure of the CISC CPU, the two also provided compiler

EDA常用双LED显示译码程序，将四位二进制数译码为七位对应于LED7位输入的高低电平信号-EDA common dual LED display decoding procedure will be four binary decoding for seven LED7 spaces corresponding to the input signal circuits

用VHDL实现视频控制程序,实现对图像的采集和压缩,-Using VHDL realize video control procedures, to achieve image acquisition and compression,

这是基于Nios II的12864液晶点亮程序，包含汉字、字符等(This is a program which is based on Nios II ,its function is light the 12864 LCD that including Chinese characters, characters)

Verilog编写的串口通讯下解码状态机(Verilog serial communication prepared under the decoder state machine)