这是一个非常实用的，非常实用，关于使用的软件，电动汽车…

本示例为基于FPGA红色飓风一代IDS-EP1C6/12开发板的USB传输，实现了pc端接收来自FPGA开发板的数据，并显示条纹，具体使用说明见解压后的说明文档。(This example is based on red hurricane generation FPGA development board' s USB transfer IDS-EP1C6/12 realized pc client receives the data from the FPGA development board and display stripes, detailed instructions, see the documentation after decompression.)

FPGA部分源代码，关于dsp48的应用，从一本很好的书上下的

用VHDL编写的4、7、40、64、84计数器，可将程序中的具体数字设成任意值。-Using VHDL written 4,7,40,64,84 counter, you can program specific figures set to any value.

REEDSOLOMON source code

通信控制中常用的脉冲宽度检测程序，VHDL模块化编成实现（原创）(communication control used in pulse width detection procedures, VHDL modular organization to achieve (original))

出租车模块设计加nios2设计cup程序代码 出租车模块设计加nios2设计cup程序代码-Taxi modular design design cup plus nios2 code taxi modular design design cup plus nios2 code

这是一个用vhdl硬件描述语言实现的乘法器而不是多路选择器-this is an implimentation of an multiplier rather than multiplexer.

键盘扫描，实现4×4键盘扫描功能，实现在数码管上显示相应的数字-Keyboard scanning, the realization of 4 × 4 keyboard scan function, the realization of digital tube display in the corresponding figure

verilog实现的1024位的大数模逆算法，引入RAM作为数据通道-verilog to achieve the 1024 Modular inverse algorithms, the introduction of RAM as a data channel

译码器，将八位输出转换为七段译码显示，相当于7448驱动译码管-Decoder, the 8 output is converted to seven segment decoding shows that the equivalent of 7448