CU设计

LS165移位寄存器的verilog语言编写(The writing of the Verilog language of LS165 shift register)

以太网的vhdl和verilog代码，供大家学习-Ethernet VHDL and Verilog code for everyone to learn

SSI转ABZ信号FPGA程序，测试完全可用(Function of SSI convert to ABZ signal,is available)

应用vhdl语言进行加法器的设计，比较器的设计，随着vhdl语言的应用越来越广泛，其重要性也更加明确。希望对大家有所帮助。-application vhdl language adder design, compared with the design, With vhdl language widely used, the importance of which was more explicit. We want to help.

《数字电路EDA入门－VHDL程序实例》---交通灯程序例子-"digital circuit EDA portal-VHDL program examples"-- traffic lights procedures example

实现4倍抽取的CIC抽取滤波器模块的Verilog实现，在对数据进行抽取之前，首先进行滤波(Extracted 4 times realize CIC decimation filter module Verilog realize that in the data collected before the first filter)

XAPP585 serdes_1_to_7 and serdes_7_to_1 data

编写 VHDL 代码为 4 x 1 多路复用器，使用下面的方法 (1) if else 语句 (2) case 语句 (3) 与声明

cpld 控制 8-32M sdram 控制器 maxII epm570实现。-CPLD control 8-32M sdram controller maxII epm570 realize.

每次开机都将次数加1 并存储到EEPROM。这样就能直观的看到机器的使用次数 用P1口 LED做为显示，次数大于256是将溢出，按复位模拟开机 或者直接通过开关开机(Each boot will add a number of times and stored to the EEPROM. So you can visually see the frequency of use of the machine as with P1 port LED display, the number is greater than 256 will overflow, analog power or press the reset switch power directly through)