CU设计

build a music player with nios 2

将FPGA设计仿真结果数据写入到txt记事本中，然后通过Matlab读取txt中的数据并显示图像(write the FPGA simulation result data into textbook,and read these data from textbook and display image in Matlab)

CAN总线的数据采集，FPGA到USB。verilog hdl语言。(CAN bus data acquisition, FPGA to the USB. verilog hdl language.)

Implement LMS vhdl code.

说明：  用于生成adams或recurdyn所需的路面不平度，用于悬架或其他的仿真(Adams or recurdyn used to generate the required road roughness for suspension or other simulation)

BT656转RGB的算法实现代码，使用VORILOG语言编写(BT656-->RGB, verilog)

A program for a simple decoder using ModelSim6

说明：  在Xilinx环境下编写的vhdl程序，实现推箱子的游戏任务，界面很漂亮。(Xilinx environment in the preparation of the VHDL program, realized the game viewing tasks, the interface is very beautiful.)

这是基于MIMO-OFDM的同步算法研究的源程序。本程序采用的极大似然估计的方法。(This is based on MIMO-OFDM synchronization algorithm source code. The program uses the method of maximum likelihood estimates. )

RapidIO：使用Avalon-ST直通接口的实现方法，可以在fpga上实现(rapidio altera)