登录
首页 » VHDL » VHDL由IEEE 1076标准定义的,IEEE标准的VHDL语言参考人…

VHDL由IEEE 1076标准定义的,IEEE标准的VHDL语言参考人…

于 2023-05-31 发布 文件大小:782.40 kB
0 150
下载积分: 2 下载次数: 1

代码说明:

VHDL is defined by IEEE Standard 1076, IEEE Standard VHDL Language Reference Manual (the VHDL LRM). The original standard was approved in 1987. IEEE procedures require that standards be periodically reviewed and either reaffirmed or revised. The VHDL standard was revised in 1993, 2000, and 2002. In each revision, new language features were added and some existing features enhanced. The aim in each revision was to improve the language as a tool for design and verification of digital systems. Since the 2002 revision, there have two parallel efforts to further develop the language. The first was the VHDL Procedural Interface (VHPI) Task Force, a subcommittee of the IEEE P1076 Working Group. The VHPI Task Force prepared an interim amendment to the standard, formally approved by IEEE in March 2007. The amendment is titled IEEE 1076c, Standard VHDL Language Reference Manual―Amendment 1: Procedural Language Application Interface.

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • VHDL描述的时钟分频电路,用途广
    VHDL描述的时钟分频电路,用途广-VHDL description of the clock divider circuit, uses widely ...
    2022-03-10 15:35:57下载
    积分:1
  • counter4b
    Vivado同步计数器VHDL设计 具有异步复位和同步预置数功能 同步计数器同步计数器同步计数器(The Vivado synchronous counter VHDL is designed with asynchronous reset and synchronous preset function, synchronous counter, synchronous counter and synchronous counter.)
    2021-03-26 14:29:13下载
    积分:1
  • 一些有用的PicoBlaze的来源。
    Some useful PicoBlaze sources.
    2022-01-26 02:08:20下载
    积分:1
  • 16位二进制转化为BCD码
    此代码可以实现16位二进制和BCD码之间的转换。(This code can realize the conversion between 16 bit binary and BCD code.)
    2018-10-31 13:31:13下载
    积分:1
  • 篮球24秒可控计时器设计
    用VHDL语言设计篮球24秒可控计时器功能说明:1.具有24秒计时、显示功能;              2.设置外部按键,完成清零、暂停、恢复控制;              3.24秒倒计时,时间间隔为1s;               4.时间到后发出报警信号,并在3s后解除。
    2022-05-28 22:06:17下载
    积分:1
  • This is an 16 bit adder using vhdl
    实现十六位加法器,是书籍上配套的应该可用-This is an 16 bit adder using vhdl
    2023-09-07 11:05:03下载
    积分:1
  • 低通FIR滤波器的设计
    利用matlab、xilinx13.4和ipcorefir编译器5.0进行了低通滤波器的设计。所附的代码将帮助您制作所需频率的低通滤波器。fir编译器有许多不同类型的规范。您可以根据您的要求提供所有规格。这里采样频率为700hz,通带频率为35hz,阻带频率为40hz。在分配完所有的值之后,您可以在matlab中生成滤波器的系数。matlab将生成.coe文件,您可以在FIR编译器中浏览该文件。它将生成一个文件,您可以在ADCU DAC代码中实例化该文件,并获得所需的输出。
    2022-02-25 01:38:04下载
    积分:1
  • polyphaseFIR_1v0
    polyphase fir dilter
    2016-02-19 21:32:07下载
    积分:1
  • 子字节的有效执行
    应用背景此文件包括执行与数学计算的子字节。查找表和组合方法已被包括在内。关键技术Xilinx XC3S400 VHDL编程语言已经使用这些代码。
    2023-05-26 21:50:03下载
    积分:1
  • fft_ex1
    基于verilog的FFT设计,使用vivado作为开发平台(Verilog based on the FFT design, the use of vivado as a development platform)
    2021-02-24 23:39:39下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载