登录
首页 » VHDL » VHDL由IEEE 1076标准定义的,IEEE标准的VHDL语言参考人…

VHDL由IEEE 1076标准定义的,IEEE标准的VHDL语言参考人…

于 2023-05-31 发布 文件大小:782.40 kB
0 155
下载积分: 2 下载次数: 1

代码说明:

VHDL is defined by IEEE Standard 1076, IEEE Standard VHDL Language Reference Manual (the VHDL LRM). The original standard was approved in 1987. IEEE procedures require that standards be periodically reviewed and either reaffirmed or revised. The VHDL standard was revised in 1993, 2000, and 2002. In each revision, new language features were added and some existing features enhanced. The aim in each revision was to improve the language as a tool for design and verification of digital systems. Since the 2002 revision, there have two parallel efforts to further develop the language. The first was the VHDL Procedural Interface (VHPI) Task Force, a subcommittee of the IEEE P1076 Working Group. The VHPI Task Force prepared an interim amendment to the standard, formally approved by IEEE in March 2007. The amendment is titled IEEE 1076c, Standard VHDL Language Reference Manual―Amendment 1: Procedural Language Application Interface.

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • weitb
    在数字通信中,通常直接从接收到的数字信号中提取位同步信号,这种直接法按其提取同步信号的方式,大致可分为滤波法和锁相法。锁相法是指利用锁相环来提取位同步信号的方法,本设计方案就是基于锁相环的位同步提取方法,能够比较快速地提取位同步时钟,并且设计简单,方便修改参数。采用Quartus II设计软件对系统进行了仿真试验,并用Altera的Cyclone II系列FPGA芯片Ep2c5予以实现。(In digital communication, usually from receiving directly in digital signal extracted a synchronized signal, the direct method according to the extraction synchronized signal way, can be roughly divided into filtering method and phase lock method. Phase lock method is using of phase locked loop to extract a synchronized signal method, the design scheme is based on phase locked loop of a synchronous extraction method and can be quickly extract a synchronous clock, and design simple, convenient modification parameter. The Quartus II design software of the system, and the simulation test Altera Cyclone II FPGA chip to achieve Ep2c5 series.)
    2020-12-01 10:39:28下载
    积分:1
  • power_control
    四轴动力模块,用一个顶模块控制,输入有:油门(20档);指令;水平仪控制指令,4个输出口(Axis power modules, with a top module control inputs are: accelerator (20 files) instruction Level control instructions, four output ports)
    2013-12-26 20:57:03下载
    积分:1
  • basic_cpu_mano_ise_vhdl
    morris mano basic vhdl code in ise
    2014-01-13 05:52:01下载
    积分:1
  • VGA
    VHDL语言实现VGA的显示彩条横条九宫格的功能。(VGA display color of the VHDL language bar Jiugongge function.)
    2013-05-07 10:04:10下载
    积分:1
  • 加法计数器的VHDL工程,程序,仿真图形
    加法计数器的VHDL工程,程序,仿真图形-adder jishuqi de VHDL FANGZHEN ,CHENGXU
    2022-01-25 14:28:29下载
    积分:1
  • xilinx平台DDR3设计教程之仿真篇_中文版教程
    DRD3在Xlinix平台上的设计教程以及仿真(DRD3 design tutorial and Simulation on Xlinix platform)
    2018-11-02 11:18:06下载
    积分:1
  • cntrlr
    verilog code for bus controller
    2014-03-19 15:17:24下载
    积分:1
  • verilog-lfsr-master
    Fully parametrizable combinatorial parallel LFSR/CRC module. Implements an unrolled LFSR next state computation. Includes full MyHDL testbench.
    2020-06-24 21:40:01下载
    积分:1
  • jishuqi
    计数器是数字系统中使用最多的时序电路,它不仅能用于对时钟脉冲计数,还可以用于分频、定时、产生节拍脉冲和脉冲序列以及进行数字运算等。(Counter is the most frequently used sequential circuit in digital system. It can be used not only for counting clock pulses, but also for frequency division, timing, generating beat pulses and pulse sequences, and performing digital operations.)
    2018-11-26 15:42:03下载
    积分:1
  • 1
    说明:  matlab code for JTAG cable checking
    2014-02-04 19:27:39下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载