Using VHDL language driver DM128* 64LCD procedures

System Generator

已经正式出版，西安电子科技大学出版社，FPGA设计及应用，作者褚振勇(Has been officially published, Xi' an University of Electronic Science and Technology Publishing House, FPGA design and application, the author Zhezhengyong)

说明：  半带滤波器，用于sigma-delta DAC中的设计(Half-band filter for sigma-delta DAC design)

《可综合的Verilog语法》国外著名大学老师编写，对于理解verilog HDL文件的可综合与不可综合会有帮助。-synthesizable Verilog syntax and semantics,by teachers from university of Cambridge,It is userful for verilog HDL design.

VHDL USB2.0接口源码,内有说明,详细.-VHDL USB2.0 interface source code, which is described in detail.

Temperature measurement Using LabVIEW FPGA, Spartan3E, PMODTMP

8051单片机VHDL内核,内有说明,很详细,值得下载-8051 VHDL core, which has made it clear that, in great detail, it is worth downloading

可YCrCb2RGB集成模块（Verilog）采用三行，它们简单的做分数运算，有流水线技术

说明：  介绍USB PHY接口中的UTMI接口， 对使用Verilog进行USB接口编程具有帮助。(This paper introduces UTMI interface in USB PHY interface. It is helpful for programming USB interface with Verilog.)

24秒倒计时系统（有跑马灯） 利用CPLD-24 seconds remaining systems (5,250) using CPLD