一个基于FPGA的数字跑表系统的设计，最小单位是百分表位。采用十进制进位。...

说明：  ADDER USING VERILOG ADDER WITH VERILOG VERILOG ADDER

用VHDL实现视频控制程序,实现对图像的采集和压缩,-Using VHDL realize video control procedures, to achieve image acquisition and compression,

CPLD imlementation of I2C BUS Controller. The description has been made by VHDL

800 x 480 / inch lcd

AD9268的配置Verilog实现，程序用于实现4通道的AD9268的配置(The 4 channel AD9268 configuration)

软件开发环境：ISE 7.1i 仿真环境：ISE Simulator 1. 这个实例实现通过ISE Simulator工具实现一个具有两个方向共八个灯的交通灯控制器； 2. 工程在project文件夹中，双击traffic.ise文件打开工程； 3. 源文件在rtl文件夹中，traffic.v为设计文件，traffic_tb.tbw是仿真波形文件； 4. 打开工程后，在工程浏览器中选择traffic_tb.tbw，在Process View中双击“Simulation Behavioral Model”选项，进行行为仿真，即可得到仿真结果。-Software development environment: ISE 7.1i simulation environment: ISE Simulator1. Realize this instance through the ISE Simulator tool to achieve a total of eight lights in both directions of traffic lights controller 2. Works project folder, double-click traffic.ise Open the project document 3. rtl source file in the folder, traffic.v for design documents, traffic_tb.tbw is the simulation waveform files 4. to open a project, the project browser, select traffic_tb.tbw, in the Process View in the double hit

同步与异步FIFO的verilog实现，包括源代码，testbench，测试以及综合通过，还有相关参考资料(Synchronous and asynchronous FIFO verilog achieve, including source code, testbench, test and integrated through, as well as related references)

SMII 到 MII 转换的VHDL代码-SMII to MII conversion of VHDL code

build a music player with nios 2

超級好用 25M~100HZ的除頻器 寫了好久 超級實用 歡迎下載(Super easy to 25M ~ 100HZ of divider wrote a long time super practical welcome to download)