LZRW1 VHDL语言，有有下

华为文档《硬件描述语言Verilog基础》-目录 原来搞VHDL，刚刚开始学Verilog。觉得这个入门的提纲不错，共享一下。 (Huawei Documents " basic Verilog Hardware Description Language" - the original directory engage in VHDL, just beginning to learn Verilog. Feel that the entry of the outline of a good, share some.)

在QuartusII运用ＡＨＤＬ语言，首先设计出PN发生器来产生一个11位的数据流在整个周期内有效数据有 =2047位；再设计状态机用来检测串行数据流中的序列。运用两个个计数器分别对PN码计数以及序列出现的次数计数。改变ＰＮ码结构可以作为通用数列检测器-QuartusII use in AHDL language, the first PN generator designed to generate a data stream 11 throughout the cycle has an effective data = 2047 re-designing the state machine used to detect the serial data stream in sequence. The use of two counters were counting on the PN code, as well as counting the number of sequences occur. Changes in the structure of PN code series can be used as general-purpose detector

4人抢答系统，可以计时20秒，20秒无人抢答则视作无人抢答。start之前抢答者视为违规抢答，违规抢答会警告选手。若有一人抢答则其他3人锁定，不可再抢答。aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa

sparc org, vhdl rtl code

说明：  使用FPGA测量频率大小，并且在数码管上进行显示(Frequency measurement using FPGA and display on digital tube)

实现DE2_115开发板上配套的500万像素cmos摄像头捕捉到的画面显示在VGA上(DE2_115 development board supporting 5,000,000 pixels cmos camera to capture the screen display in VGA)

CPLD的VerilogHDL总线代码,在EPM7128SLC84-10+Quartus4平台上运行通过.-CPLD bus Verilog HDL code, the PLD-10 Quartus4 platform to run through.

用VHDL编写的JK触发器  用VHDL编写的JK触发器 用VHDL编写的JK触发器

这是一个vhdl代码的进位选择加法器及其工作100%。

8051MCU在FPGA上实现的源代码，用VHDL语言编写-8051MCU in the FPGA to achieve the source code, using VHDL language