一个用FPGA语言设计数字秒表的程序，有相关的源程序和说明

AD采集模块,设计模块采集AD5270的输出数据(AD Collection module Design module to collect the output data of AD5270 )

10G高速以太网mac VERILOG源码 可仿真可实现(10G high speed Ethernet MAC verilog code can be used for synthesis or inplementation)

本例程位于 VMD642_CPLD目录中。 使用 CPLD 实现辅助译码、LED 指示灯控制、看门狗等各种逻辑控制电路。源程序使 用 Verilog HDL书写，编译开发系统使用 Cypress公司的 Warp 6.3。(This routine is located VMD642_CPLD directory. Using CPLD implementation auxiliary decoding, LED indicator control, watchdog, and other logic control circuitry. Written using Verilog HDL source code, the compiler development system using Cypress' s Warp 6.3.)

在MATLAB下自编实现快速傅里叶分析，(Fast fft own procedures, faster than the system call fft slowe)

mc8051 很好的学习资料 官网的绝对权威-mc8051 a good learning materials in absolute authority of the official website

fpga串口的发送程序基于verilog语言拿走不用谢。(The sending program of FPGA serial port is based on Verilog language.)

Triscend supports the use of the Model Technology ModelSim logic simulator for VHDL simulation of designs implemented in the Configurable System Logic (CSL) portion of a Triscend device.

FPGA实现BPSK调制，带Modelsim仿真，实际系统测试通过，载波信号，调制波信号频率可调(FPGA implementation BPSK modulation with Modelsim simulation, the actual system test, the carrier signal, modulated wave signal frequency adjustable)

单口RAM带CLR信号的verilog程序。很详细的.(Single-port RAM with a CLR signal)

An Alarm Project Writen in VHDL for FPGA Devices